Structure of electrically programmable read-only memory cells an

Structure of horizontal surrounding gate flash memory cell

Structure to inspect high/low of memory cell threshold...

Structure to recover a portion of a partially functional embedde

Structures and methods of preventing an unintentional state...

Structures for wafer level test and burn-in

Structures for wafer level test and burn-in

Sub-block redundancy replacement for a giga-bit scale DRAM

Sub-column-repair-circuit

Sub-word line drivers for integrated circuit memory devices and

Subarray architecture with partial address translation

Substrate bias generator for use in dynamic random access memory

Substrate bias generator in a dynamic random access memory with

Substrate bias voltage generating circuit including an internal

Subtraction circuits and digital-to-analog converters for...

Summing circuit with biased inputs and an unbiased output

Supervoltage circuit

Supply line controlled sense amplifier

Supplying voltage to a bit line of a memory device

Support circuitry for multi-port systems