Structure of horizontal surrounding gate flash memory cell

Details Structure of horizontal surrounding gate flash memory cell Structure of horizontal surrounding gate flash memory cell

2001-12-21

2003-07-01

Nelms, David (Department: 2818)

Static information storage and retrieval

Read/write circuit

Differential sensing

Reexamination Certificate

active

06587396

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to a process for manufacturing a flash memory, and more particularly, to a structure of a horizontal surrounding gate (HSG) flash memory cell.
BACKGROUND OF THE INVENTION
As semiconductor process technologies continue improving, computers, telecommunication products, network products, and information appliances (IA) are developed vigorously. To scale down the size of semiconductor devices is the primary motivation to drive the semiconductor process technologies. By scaling down devices size, the performance, such as the changing speed of devices and the power consumption of devices, can then be improved, and the functions thereof, such as data storage, logic operation, and information processing, can be enhanced. Therefore, the cost can be reduced. Especially, for semiconductor memory devices that have a very important share in the market have strict demands about the diminution of device size.
According to the functional differences, memory devices can be divided into a random access memory (RAM) and a read only memory (ROM). The ROM does not lose the stored data even with the interruption of supplying power and is thus called as a nonvolatile memory. Contrarily, the RAM must keep the supplying power uninterruptedly for reserving the stored data and is thus called as a volatile memory. In addition, according to the ways for storing data, the ROM can be further divided into a mask read only memory (MROM), an erasable programmable ROM (EPROM), an electrically erasable programmable ROM (EEPROM), and a flash memory, etc. Also, according to the structural difference, the RAM can be further divided into a dynamic RAM (DRAM) and a static RAM (SRAM).
As the increasing popularization of portable electric devices, imperious demands for light, handy, and dependable storage devices are induced. Regardless of digital cameras, notebooks, personal digital assistants (PDA), digital music players, or mobile phones, etc, they all need a dependable and convenient method to store and transmit data. Because the data stored in a flash memory can be kept after the power is shut off, flash memory devices are widely applied in the portable electric devices.
Referring to
FIG. 1
,
FIG. 1
shows a cross-sectional view of a conventional stacked gate flash memory cell structure. A flash memory cell
100
is formed on a semiconductor substrate
102
, and a tunneling oxide layer
108
, a floating gate
110
, a dielectric layer
112
, and a control gate
114
of the flash memory cell
100
are stacked and formed on the semiconductor substrate
102
in sequence. A source
104
and a drain
106
of the flash memory cell
100
are formed by a thermal diffusion method or an ion implantation method to dope ions into the substrate
102
. Typically, the floating gate
110
and the control gate
114
are composed of polysilicon, and thus the dielectric layer
112
is called as an inter-poly dielectric (IPD) layer. Besides, the dielectric layer
112
is usually formed by stacking three material layers, i.e. oxide
itride/oxide (ONO), thereby to provide a better blocking ability for preventing the chargers within the floating gate
110
from entering the control gate
114
.
Typically, the programming of the flash memory cell
100
is performed by a channel hot electron injection (CHEI) method. For example, the channel hot electron injection method is to set the substrate
102
and the source
104
to 0 V, and the drain
106
to about 3 V, and to connect the control gate
114
to a power of high voltage, such as 12 V. At this time, the electrons of the source
104
are driven by the voltage of the drain
106
to pass through the channel region
105
and move toward the drain
106
, and the energy of electrons is increased by the acceleration from the high channel electric field. Especially in the channel region
105
that is adjacent to the drain
106
, the energy of electrons is greatly increased, thereby inducing the hot electron effect. As a result of the hot electron effect, the electrons have enough energy to exceed the potential barrier of the tunneling oxide layer
108
. At the same time, the attraction resulted from the high voltage of the control gate
114
drives the electrons to pass through the tunneling oxide layer
108
and inject into the floating gate
110
.
In addition, the erasing action of the flash memory cell
100
is performed by a Fowler-Nordheim (FN) tunneling effect. The FN tunneling effect erasing method can be divided into a channel erasing method and a source/drain erasing method. In the channel erasing method, the control gate
114
is supplied with a negative voltage or is grounded, and the channel region
105
is supplied with a high voltage, such as 12 V, thereby attracting the electrons of the floating gate
110
into the channel region
105
to complete the data erasing. In the source/drain erasing method, the control gate
114
is supplied with a negative voltage or is grounded, and the source
104
and/or the drain
106
are supplied with a high voltage, such as 12 V, thereby attracting the electrons of the floating gate
110
into the source
104
and/or the drain
106
to complete the data erasing.
As semiconductor process technologies continue enhancing, although the supplied voltage needed for performing the programming and erasing of the flash memory cell
100
is reduced, yet the electric field for programming and erasing the flash memory cell
100
still needs the same intensity. Without changing the programming/erasing voltage of the flash memory cell
100
, it is very difficult to achieve the desired voltage of programming/erasing while the supplied voltage is reduced. At present, there are two methods can be used to reduce the programming/erasing voltage of the flash memory cell
100
. The first method is to decrease the thickness of the tunneling oxide layer
108
, and the second method is to increase the capacitor coupling ratio between the control gate
114
and the floating gate
110
. Since the thickness of the tunneling oxide layer
108
multiplies the electric field used to program/erase the flash memory cell
100
is proportional to the voltage for programming/erasing the flash memory cell
100
, decreasing the thickness of the tunneling oxide layer
108
can reduce the voltage for programming/erasing the flash memory cell
100
. However, in order to keep the reliability of the flash memory cell
100
, the thickness of the tunneling oxide layer
108
is preferred to be more than 80 Å, and is about 100 Å more preferably. Hence, there is not much room left for decreasing the thickness of the tunneling oxide layer
108
. In addition, increasing the capacitor coupling ratio between the control gate
114
and the floating gate
110
can increase the floating gate
110
voltage coupled from the control gate
114
, so that the voltage needed to be supplied to program/erase the flash memory cell
100
can be reduced. However, in the typical flash memory cell
100
process, increasing the capacitor coupling ratio between the control gate
114
and the floating gate
110
usually leads to an increase in the size of the flash memory cell
100
and the process cost.
Furthermore, since there is not much room left for decreasing the thickness of the tunneling oxide layer
108
, when the supplied voltage is reduced, the electrons ejecting from the source
104
though the channel region
105
to the drain
106
cannot be controlled effectively. Especially, as the device size continues reducing to make the gate region decrease continuously, so that the leakage current of the sub-channel area far from the gate under the channel region
105
is getting more serious. Particularly, for the flash memory cell
100
using the source/drain erasing method, the source
104
/drain
106
need a larger junction depth. Thus, the leakage current is getting worse.
SUMMARY OF THE INVENTION
According to the aforementioned conventional flash memory cell structure, the leakage current between a source and a drain is getting worse as de

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