Structure to inspect high/low of memory cell threshold...

Details Structure to inspect high/low of memory cell threshold... Structure to inspect high/low of memory cell threshold...

2001-04-11

2002-12-24

Nelms, David (Department: 2818)

Static information storage and retrieval

Read/write circuit

Differential sensing

C365S185130, C365S185200, C365S185240, C365S189090, C365S189110

Reexamination Certificate

active

06498757

ABSTRACT:

CROSS-REFERENCE TO RELATED APPLICATION
This application claims the priority benefit of Taiwan application serial no. 89124861, filed Nov. 23, 2000.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates in general to a structure to inspect high/low of a memory cell threshold voltage. More particularly, the invention relates to a structure to inspect high/low of a memory cell threshold voltage using a current mode sense amplifier.
2. Description of the Related Art
The conventional flash memory is basically designed in a voltage mode. Therefore, to separate a high threshold voltage memory cell from a low threshold voltage memory cell, the current of the selected memory cell has to be converted to voltage. A reference voltage generated by a reference memory cell is compared to the voltage of a selected memory cell. If the output result is “0”, the selected memory cell has a high threshold voltage. On the contrary, if the output result is “1”, the selected memory cell has a low threshold voltage.
FIG. 1
shows a conventional structure to compare a reference memory cell near the bit line voltage with a selected memory cell. The structure comprises a bit line decoder
10
, a word line decoder
12
, a memory cell
14
, a current-to-voltage converter
16
, a reference word line
18
, a reference memory cell
20
, a reference voltage
22
and a voltage sense amplifier
24
.
An output of the bit line decoder
10
is coupled to a drain of the memory cell
14
. An output of the word line decoder
12
is coupled to a gate of the memory cell
14
. A source of the memory cell
14
is coupled to a ground voltage Vss. The output of the bit line decoder
10
is further coupled to the current-to-voltage converter
16
. A gate of the reference memory cell
20
at the other side is coupled to the reference word line
18
. A drain of the reference memory cell
20
is coupled to another bit line decoder (not shown), and a source thereof is coupled to the ground voltage Vss. A drain of the reference memory cell
20
is coupled to the reference voltage
22
. That is, both the drain of the reference memory cell
22
and the current-to-voltage converter
16
are coupled to the voltage sense amplifier
24
.
The above structure is used to detect the Vt distribution of memory cells on a chip, so as to trace the problems in fabrication process and to maintain a correct access. However, the structure is restricted with the variation range of VDD. When the variation of VDD exceeds ±10%, the word line voltage dependent on the VDD has a significant variation. Thus, the reference voltage bias node applied to the voltage sense amplifier
24
is shifted to cause an error access. Therefore, the conventional structure is not suitable for use in a flash memory with a voltage source having a wide variation range. In addition, using the comparison of voltage, the current of the selected memory cell has to be converted into voltage (the current-to-voltage converter
16
is required), so that the reading speed is slowed down. The addition of reference word line
18
and the reference memory cell
20
increases the occupied area.
SUMMARY OF THE INVENTION
The invention provides a structure to inspect high/low of memory cell threshold voltage using a current mode sense amplifier. A current is input for comparison. When the high threshold voltage is selected, there is no current generated. When the low threshold voltage is selected, a current is generated. Therefore, one does not need to consider the situation of exceeding amplitude. In addition, the current-to-voltage conversion is not required, so that the reference word line and the reference memory cell are not required either. The consumed area is reduced.
The invention provides a structure to inspect high/low of memory cell threshold voltage using current mode sense amplifier. The structure comprises a selected memory cell, a reference current generator and a current sense amplifier.
A gate of the selected memory cell receives a stabilized voltage. A source of the selected memory cell is coupled to a ground voltage, and a drain of the selected memory cell is coupled to a reference current. The current sense amplifier receives the memory cell current of the selected memory cell and the reference current to perform the operation, and to output a sense amplified signal.
The structure may further include a word line decoder to generate a word line voltage and a stabilized voltage generator to generate a fixed voltage. The fixed voltage is a voltage with a small variation output from the word line after voltage stabilization. The structure may further comprise a potential shifter to output a potential signal after receiving the word line voltage and the fixed voltage. In addition, the memory cell current is generated by a bit line decoder. The bit line decoder is coupled to a drain of the selected memory cell.
The current sense amplifier comprises a plurality of PMOS transistors, a plurality of NMOS transistors, a plurality of control valves and a plurality of inverters. A first PMOS transistor has a source connected to a high voltage and a gate connected to an activation signal. A second PMOS transistor has a source coupled to a drain of the first PMOS transistor. A drain of a first NMOS transistor is coupled to a gate and a drain of the second PMOS transistor. A gate of the first NMOS transistor is coupled to a frequency band interstitial voltage to generate a reference current. A third PMOS transistor has a source coupled to the drain of the first PMOS transistor, and a gate coupled to the gate of the second PMOS transistor. A first control valve comprises a first input/output terminal, a second input/output terminal and a first control operation terminal. The first input terminal is coupled to the drain of the third PMOS transistor. The first control operation terminal receives an erase inspection signal to control the generation of an erase inspection current. A fourth has a source coupled to the drain of the first PMOS transistor, a gate coupled to the gate of the second PMOS transistor. The first inverter receives the erase inspection signal and outputs an inverse erase inspection signal. A second control valve comprises a third input/output terminal, a fourth input/output terminal and a second control operation terminal. The third input/output terminal is coupled to a drain of the fourth PMOS transistor. The second control operation terminal receives the inverse erase inspection signal to control the generation of a reading and programming confirming current. A drain of a second NMOS transistor is coupled to the second input/output terminal of the first control valve and the fourth input/output terminal of the second control valve. A source of the second NMOS transistor is to receive a memory cell current. A second inverter has an input terminal coupled to the source of the second NMOS transistor, and an output coupled to the gate of the second NMOS transistor.
A fifth PMOS transistor has a source coupled to a high voltage, a gate and a drain coupled to the second input/output terminal of the first control valve and the fourth input/output terminal of the second control valve. A sixth PMOS transistor comprises a source coupled to the high voltage and a gate coupled to the gate of the fifth PMOS transistor. A third NMOS transistor comprises a drain and a gate coupled to the drain of the fifth PMOS transistor. A drain of a fourth NMOS transistor is coupled to a drain of the sixth PMOS transistor, and a gate of the fourth NMOS transistor is coupled to the gate of the third NMOS transistor. A third inverter receives the activation signal and outputs an inverse activation signal. A fifth NMOS transistor comprises a drain coupled to a source of the third NMOS transistor and a source of the fourth NMOS transistor, and a gate to receive the inverse activation signal. A seventh PMOS transistor comprises a source coupled to the high voltage and a gate to receive the activation voltage. An eighth PMOS transistor comprises a source coupled to a drai

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