Sub-block redundancy replacement for a giga-bit scale DRAM

Details Sub-block redundancy replacement for a giga-bit scale DRAM Sub-block redundancy replacement for a giga-bit scale DRAM

1998-09-30

1999-11-02

Nelms, David

Static information storage and retrieval

Read/write circuit

Bad bit

36518908, 36523006, 365210, G11C 700

Patent

active

059782919

ABSTRACT:
A sub-block redundancy replacement memory configuration for repairing a plurality of faulty memory arrays, each consisting of a plurality of memory cells arranged in a first matrix formation, supported by first row decoders and first sense amplifiers, by combining at least two with at most n-1 out n sub-block redundancy arrays, each consisting of a plurality of redundancy memory arrays arranged in a second matrix, and supported by second row decoders and second sense amplifiers. Since additional sub-block redundancy arrays are available, it is possible to repair a defective memory array even if one or more block faults are present in the memory. The number of cells in the redundancy arrays is less than the number of cells in the memory arrays, substantially reducing the silicon overhead. Optionally, the sub-block redundancy memory arrays are distributed within at least two units, each consisting of a plurality of memory arrays, at least one sub-block redundancy array and corresponding columns decoders. The columns decoders are activated as a result of a redundancy match detection which determines whether a memory array or a sub-block redundancy memory array in any unit is activated.

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