NOR type mask ROM with an increased data flow rate
Operating an electronic device having a vertical gain cell...
Parallel electrode memory
Pattern layout of power source lines in semiconductor memory dev
Pin configuration changing circuit, base chip and system in...
Placement of clock circuits for semiconductor memory
Pore structure for programmable device
Power bussing layout for memory circuits
Power line layout
Power source circuit and wiring group for semiconductor memory d
Process variation compensated multi-chip memory package
Processor module with dual-bank SRAM cache having shared capacit
Production method for semiconductor storage device and...
Random access memory and an improved bus arrangement therefor
Read only memory cell for storing a multiple bit value
Reconfigurable memory arrays
Reduced area sense amplifier isolation layout in a dynamic...
Reduced area sense amplifier isolation layout in a dynamic...
Reduced area sense amplifier isolation layout in a dynamic...
Reference cell layout with enhanced RTN immunity