Pattern layout of power source lines in semiconductor memory dev

Static information storage and retrieval – Format or disposition of elements

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365226, H01L 2710

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052933342

ABSTRACT:
A first power source line is formed around a memory area having a memory cell array, column decoder, row decoder and sense amplifier formed therein. The first power source line is applied with a potential which is obtained by lowering a power source voltage supplied from the exterior. A second power source line is formed in the surrounding region of the first power source line. The second power source line is applied with a ground potential. A first peripheral circuit driven by a voltage between the lowered potential and the ground potential is disposed in an area between the first and second power source lines. The first peripheral circuit is a circuit used for the memory area. A third power source line is formed in the surrounding region of the second power source line. The third power source line is applied with a power source potential supplied from the exterior. A second peripheral circuit driven by a voltage between the power source potential and the ground potential is disposed in an area between the second and third power source lines. The second peripheral circuit is a circuit used for an external circuit of a chip.

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