Random access memory and an improved bus arrangement therefor

Details Random access memory and an improved bus arrangement therefor Random access memory and an improved bus arrangement therefor

1995-03-13

1996-05-14

Nelms, David C.

Static information storage and retrieval

Format or disposition of elements

365 63, 36523003, G11C 700

Patent

active

055174426

ABSTRACT:
The present invention is a bus arrangement for a wide I/O Random Access Memory (RAM). The bus arrangement includes a global address bus which drives row/column predecoders and redundancy comparators placed at each edge of the memory array. Two banks of sixteen data I/O (DQs), one bank for each half chip, are placed at either end of the chip providing up to a .times.32 I/O organization. The main Read/Write Data lines (RWD) are more densely populated near the chip edge than the chip center to provide .times.4 and .times.8 options, as well. A local address bus is in the open space between the RWDs to redrive the global address lines at their quarter points.

REFERENCES:
patent: 4660174 (1987-04-01), Takemae
patent: 4701885 (1987-10-01), McElroy
patent: 4796224 (1989-01-01), Kawai
patent: 5142492 (1992-08-01), Shimizu
patent: 5367480 (1994-11-01), Matsumiya

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