Power bussing layout for memory circuits

Details Power bussing layout for memory circuits Power bussing layout for memory circuits

1996-04-10

1997-11-11

Nelms, David C.

Static information storage and retrieval

Format or disposition of elements

365226, 365 63, G11C 502, G11C 506

Patent

active

056871082

ABSTRACT:
A layout technique that improves the bussing of power lines in multi-array memory circuits is disclosed. The present invention utilizes regions inside memory arrays that are otherwise unused by a given metal layer to bus the power to the circuitry between the arrays. The layout technique allows wide power buses to cross over memory arrays extending perpendicular to word lines along wide areas used for word line contacts.

REFERENCES:
patent: 4945513 (1990-07-01), Ueda
patent: 5293559 (1994-03-01), Kim
patent: 5321646 (1994-06-01), Tomishima
patent: 5325336 (1994-06-01), Tomishima

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