Reference cell layout with enhanced RTN immunity

Details Reference cell layout with enhanced RTN immunity Reference cell layout with enhanced RTN immunity

2007-04-27

2009-06-23

Mai, Son L (Department: 2827)

Static information storage and retrieval

Format or disposition of elements

C365S210140, C365S210150

Reexamination Certificate

active

07551465

ABSTRACT:
A reference cell layout includes a plurality of active areas, in parallel to each other, and a first contact of the active areas, and a first gate, the first contact shorting the active areas. A memory device includes the reference cell layout and a corresponding array of memory cells having active areas sized substantially identical to the active areas of the reference cell layout and plural second contacts respectively contacting the active areas of the memory cells.

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patent: 2001/0033510 (2001-10-01), Allen et al.
patent: 2003/0012064 (2003-01-01), Beretta
patent: 2007/0109832 (2007-05-01), Hou et al.
Kurata, H., et al., “The Impact of Random Telegraph Signals on the Scaling of Multilevel Flash Memories,” 2006 Symposium on VLSI Circuit, pp. 1-2.

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