Placement of clock circuits for semiconductor memory

Details Placement of clock circuits for semiconductor memory Placement of clock circuits for semiconductor memory

1981-02-20

1985-03-19

Popek, Joseph A.

Static information storage and retrieval

Format or disposition of elements

365 63, G11C 1140

Patent

active

045063478

ABSTRACT:
A dynamic random access memory (10) is fabricated on a substrate (12) and is divided into memory sections (14, 16). Memory cells (46) are connected to bit lines (18-28, a and b), which are organized into pairs that are connected to respective sense amplifiers (34-44). A row clock circuit (52) generates clock signals to enable the addressed word line. Additional clock signals are generated by other clock circuits (56, 58). A charge pump circuit (78, 80) produces a substrate bias and includes a free running oscillator. The signal generation circuits (52, 56, 58, 78, 80) produce signal transitions which are coupled by parasitic capacitors (66-76, 81-88) into the bit lines (18-28, a and b). The clock circuits are fabricated in a symmetrical placement in relation to the bit lines (18-28, a and b) and sense amplifiers (34-44) such that the transient signals capacitively coupled from the clock circuits into the bit lines have a very low differential mode amplitude. The reduced differential mode interference from the clock circuits permits the sense amplifiers (34-44) to more accurately read the states of the memory cells (46).

REFERENCES:
patent: 4072932 (1978-02-01), Kitagawa et al.
patent: 4161791 (1979-07-01), Leach
patent: 4255679 (1981-03-01), White, Jr. et al.

Affiliated with

Also associated with

Rating

Placement of clock circuits for semiconductor memory does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Placement of clock circuits for semiconductor memory, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Placement of clock circuits for semiconductor memory will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-756535