NOR type mask ROM with an increased data flow rate

Details NOR type mask ROM with an increased data flow rate NOR type mask ROM with an increased data flow rate

2001-08-16

2002-05-14

Dinh, Son T. (Department: 2824)

Static information storage and retrieval

Format or disposition of elements

C365S063000, C365S185110, C365S185130

Reexamination Certificate

active

06388910

ABSTRACT:

BACKGROUND OF INVENTION
1. Field of the Invention
The present invention relates to a mask ROM, and more particularly, to a NOR type mask ROM with an increased data flow rate.
2. Description of the Prior Art
Data transmission speed is one of the most important demands for ROM devices. Therefore, a lot of recent researches have concentrated in the area of increasing the data transmission speed of ROM devices. Please refer to
FIGS. 1 and 2
.
FIG. 1
is a circuit diagram of a prior art NOR-type mask ROM device
10
.
FIG. 2
shows a layout of the ROM device
10
. The ROM device
10
comprises a plurality of main bit lines ML
1
-ML
5
formed in parallel with each other, a plurality of first sub-bit lines
12
connected to the main bit lines ML
1
-ML
5
through bit line contacts
14
, a plurality of second sub-bit lines SB
1
-SB
9
formed in parallel with the main bit lines ML
1
-ML
5
, a plurality of word lines WL
1
-WL
32
formed in perpendicular to the main bit lines ML
1
-ML
5
, a plurality of main bank selection lines BS
1
-BS
3
formed in parallel with the word lines WL
1
-WL
32
for selecting a memory block such as block
1
, block
2
and block
3
, and a plurality of sub-bank selection lines BSO, BSE formed within each memory block for selectively connecting neighboring second sub-bit lines SB
1
-SB
9
so as to select a corresponding sub-bank.
In
FIG. 2
, a word line running across two neighboringsecond sub-bit lines SB
1
-SB
9
forms a data transistor. A main bank selection line or a sub-bank selection line running across two neighboring sub-bit lines forms a main bank selection transistor or a sub-bank selection transistor. The selection transistors designated with an “S” are maintained in the on-state when a power source voltage V
CC
is applied thereto. The selection transistors not designated with an “S” are maintained in the off-state even if a power source voltage V
CC
is applied thereto.
The operation of the ROM device
10
is as follows; Suppose the main bit line ML
3
is grounded, the power source voltage V
CC
is applied to the main bit line ML
2
and BS
1
, BSO and WL
16
to select the block
1
, a sub-bank corresponding to the sub-bank selection line BSO and the word line WL
16
, the current in the main bit line ML
2
will flow through the bit line contact
14
a
, the first sub-bit line
12
a
and the selection transistor Sa to the second sub-bit line SB
5
. If the power source voltage V
CC
can turn on the data transistor T, the current in the second sub-bit line BS
5
will continue to flow through the data transistor T, the second sub-bit line SB
4
, the selection transistor Sb, the second sub-bit line SB
3
, the selection transistor Sc, the first sub-bit line
12
b
and the bit line contact
14
b
to the main bit line ML
3
. If the power source voltage V
CC
can not turn on the data transistor T, the second sub-bit line SB
4
will remain disconnected from the second sub-bit line SB
5
, thus, the current in the second sub-bit line BS
5
willnot flow to the main bit line ML
3
. Therefore, by checking current from the main bit line ML
3
after a time period, the data stored in the data transistor T can be retrieved.
The ROM device
10
, however, has some drawbacks. First, each of the selection transistors has a very small channel width W. Therefore, transmitting current across the selection transistors takes a long time. Moreover, the second sub-bit line such as SB
5
is positioned between two first sub-bit lines
12
a
,
12
c
. That is, the second sub-bit line SB
5
is very close to the first sub-bit line
12
c
. This short distance may result in leakage of current from the second sub-bit line SB
5
to the unrelated first sub-bit line
12
c
thus further reducing transmission speed of current and interfering other portions of the ROM device
10
.
SUMMARY OF INVENTION
In view of the foregoing, it is a primary objective of the present invention to provide a NOR type mask ROM with an increased data flow rate and a reduced interference between different portions of the mask ROM to solve the above-mentioned problems. According to the claimed invention, the NOR type mask ROM includes a plurality of main bit lines formed in parallel with each other, a plurality of first sub-bit lines connected to the main bit lines through bit line contacts, a plurality of T-shaped second sub-bit lines each having a vertical arm formed in parallel with the main bit lines, and a horizontal arm formed in perpendicular with the vertical arm, a plurality of third sub-bit lines each formed in parallel with the main bit lines and between vertical arms of two neighboring second sub-bit lines, a plurality of word lines formed in perpendicular with the main bit lines, a plurality of main bank selection lines formed in parallel with the word lines for selecting a memory block, and a plurality of sub-bank selection lines formed within each memory block for selectively connecting neighboring second and third sub-bit lines so as to select a corresponding sub-bank.
It is therefore an advantage of the claimed invention t hat the NOR type m ask ROM comprises T-shaped second sub-bit line s which greatly increase channel widths of selection transistors and are formed far away from the unrelated first sub-bit lines to reduce interferences between unrelated portion of the mask ROM. These and other objectives and advantages of the present invention will no doubt become obvious to those of ordinary skill in the art after having read the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings.


REFERENCES:
patent: 5349563 (1994-09-01), Iwase
patent: 5825683 (1998-10-01), Chang
patent: 5923606 (1999-07-01), Lee et al.
patent: 6128210 (2000-10-01), Suminaga et al.
patent: 6226214 (2001-05-01), Choi

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