Process variation compensated multi-chip memory package

Details Process variation compensated multi-chip memory package Process variation compensated multi-chip memory package

2008-11-04

2011-11-08

Phan, Trong (Department: 2827)

Static information storage and retrieval

Format or disposition of elements

C365S052000, C365S063000, C365S194000, C365S226000, C365S230030, C365S233100, C365S233130

Reexamination Certificate

active

08054663

ABSTRACT:
A multi-chip package memory includes an interface chip generating at least one reference signal defined in relation to a reference process variation, and a stacked plurality of memory chips electrically connected to the interface chip via a vertical connection path and receiving the reference clock signal via the vertical connection path, wherein each one of the stacked plurality of memory chips is characterized by a process variation and actively compensates for said process variation in relation to the reference signal.

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