Static information storage and retrieval – Format or disposition of elements
Reexamination Certificate
2011-01-04
2011-01-04
Ho, Hoai V (Department: 2827)
Static information storage and retrieval
Format or disposition of elements
C365S063000, C365S226000, C029S592100
Reexamination Certificate
active
07864555
ABSTRACT:
A pair of power supply lines that are orthogonal to the border with the cell array are placed, for each one-bit processing circuit of the data processing unit, in a semiconductor storage device such as SRAM or the like comprising a data processing unit for writing data to memory cells and reading it therefrom, a row decode unit for driving the word lines of the memory cells, and a timing control unit for generating a control pulse for the data processing unit, all of which are arranged around the circumference of a cell array in which memory cells are arrayed in a grid-like fashion. MOS transistors are placed between the power supply lines in such a position that the principal axis direction of the gate pattern is orthogonal to the two aforementioned wirings, and are closely arrayed in the longitudinal direction of the power supply lines.
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Inage Mayumi
Ito Gaku
Iwata Akio
Fujitsu Limited
Ho Hoai V
Norman James G
Staas & Halsey , LLP
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