Power line layout

Details Power line layout Power line layout

2007-11-09

2010-10-05

Hoang, Huan (Department: 2827)

Static information storage and retrieval

Format or disposition of elements

C365S063000, C365S226000

Reexamination Certificate

active

07808804

ABSTRACT:
A power line layout for a semiconductor device includes a memory cell region, a plurality of wordline enable signal lines in the memory cell region, a plurality of first power lines arranged between the wordline enable signal lines in the memory cell region, and a plurality of second power lines arranged perpendicular to the first power lines in the memory cell region to form a mesh arrangement of first and second power lines.

REFERENCES:
patent: 6765815 (2004-07-01), Fujisawa et al.
patent: 6765844 (2004-07-01), Fujisawa et al.
patent: 7161823 (2007-01-01), Lee et al.
patent: 2002/0057129 (2002-05-01), Horiguchi et al.
patent: 2005/0248042 (2005-11-01), Lee et al.
patent: 2006/0126416 (2006-06-01), Eun et al.
patent: 2004-006479 (2004-01-01), None
patent: 10-2001-0002215 (2001-01-01), None
patent: 10-2005-0115196 (2005-12-01), None
patent: 10-2006-0000358 (2006-01-01), None
patent: 10-2006-0066827 (2006-06-01), None

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