Distributing CFI devices in existing decoders
Divided bit line system for non-volatile memory devices
Divided bitline flash memory array with local sense and...
Division-based sensing and partitioning of electronic memory
DMOS device with a programmable threshold voltage
Double boosting scheme for NAND to improve program inhibit...
Double byte select high voltage line for EEPROM memory block
Double poly split gate PMOS flash memory cell
Double polysilicon EEPROM cell and corresponding manufacturing p
Double programming methods of a multi-level-cell nonvolatile...
Double-bit non-volatile memory unit and corresponding data...
Double-bit non-volatile memory unit and corresponding data...
Drain bias for non-volatile memory
Drain excluded EPROM cell
Drain pump for flash memory
Drain side sensing scheme for virtual ground flash EPROM...
DRAM and SRAM memory cells with repressed memory
DRAM cells with repressed floating gate memory, low tunnel...
DRAM cells with repressed floating gate memory, low tunnel...
Drift compensation in a flash memory