Double byte select high voltage line for EEPROM memory block

Details Double byte select high voltage line for EEPROM memory block Double byte select high voltage line for EEPROM memory block

2007-12-04

2007-12-04

Elms, Richard T. (Department: 2824)

Static information storage and retrieval

Floating gate

Particular connection

C365S238000, C365S185230

Reexamination Certificate

active

11301401

ABSTRACT:
A byte select circuit of a memory cell array wherein each column of the memory cell array has two byte select lines. A first byte select line is coupled to the even numbered rows in the column and a second byte select line is coupled to the odd numbered rows in the column. The second byte select line is configured to be driven to a low voltage level when the first byte select line is driven to a high voltage level, thereby minimizing or eliminating any parasitic voltage coupling between adjacent rows of memory cells.

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