Divided bitline flash memory array with local sense and...

Details Divided bitline flash memory array with local sense and... Divided bitline flash memory array with local sense and...

2011-07-19

2011-07-19

Luu, Pho M (Department: 2824)

Static information storage and retrieval

Floating gate

Particular biasing

C365S185130, C365S185330

Reexamination Certificate

active

07983091

ABSTRACT:
A flash memory array and a method for performing read operation therein are disclosed. The flash memory array comprises a plurality of memory segment, a data cache and a plurality of data handlers coupled between a pair of memory segment and between a memory segment and the data cache. A read operation of selected bitlines of a selected memory segment is performed by a segment data handler coupled to the selected memory segment locally and the read data is transmitted to the data cache. A segment data handler is configured to get read data from the selected bitlines by first pre-charging the bitlines and sensing the bitlines. Further, the read data is transmitted to the data cache through all of the segment data handlers in a sequential manner, if present between the selected memory segment and the data cache.

REFERENCES:
patent: 6381671 (2002-04-01), Ayukawa et al.
patent: 6928003 (2005-08-01), Miura
Kobayashi,S, et al “A 3.3V—Only 16Mb DINaR Flash Memory” ISSCC95 digest of technical papers, pp. 122-123, Feb. 1995.

Affiliated with

Also associated with

Rating

Divided bitline flash memory array with local sense and... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Divided bitline flash memory array with local sense and..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Divided bitline flash memory array with local sense and... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2637941