Static information storage and retrieval – Floating gate – Particular connection
Reexamination Certificate
2001-10-23
2003-01-21
Elms, Richard (Department: 2824)
Static information storage and retrieval
Floating gate
Particular connection
C365S185210
Reexamination Certificate
active
06510082
ABSTRACT:
FIELD OF INVENTION
The present invention relates generally to memory systems and in particular, to virtual ground flash EPROM memory array systems and methods to eliminate the effects of charge sharing leakage currents to adjacent bits and loss in transient sense current during memory cell current read operations, resulting in substantially improved signal margins.
BACKGROUND OF THE INVENTION
Flash and other types of electronic memory devices are constructed of thousands or millions of memory cells, adapted to individually store and provide access to data. A typical memory cell stores a single binary piece of information referred to as a bit, which has one of two possible states. The cells are commonly organized into multiple cell units such as bytes which comprise eight cells, and words which may include sixteen or more such cells, usually configured in multiples of eight. Storage of data in such memory device architectures is performed by writing to a particular set of memory cells, sometimes referred to as programming the cells. Retrieval of data from the cells is accomplished in a read operation. In addition to programming and read operations, groups of cells in a memory device may be erased, wherein each cell in the group is programmed to a known state.
The individual cells are organized into individually addressable units or groups such as bytes or words, which are accessed for read, program, or erase operations through address decoding circuitry, whereby such operations may be performed on the cells within a specific byte or word. The individual memory cells are typically comprised of a semiconductor structure adapted for storing a bit of data. For instance, many conventional memory cells include a metal oxide semiconductor (MOS) device, such as a transistor in which a binary piece of information may be retained. The memory device includes appropriate decoding and group selection circuitry to address such bytes or words, as well as circuitry to provide voltages to the cells being operated on in order to achieve the desired operation.
The erase, program, and read operations are commonly performed by application of appropriate voltages to certain terminals of the cell MOS device. In an erase or program operation the voltages are applied so as to cause a charge to be stored in the memory cell. In a read operation, appropriate voltages are applied so as to cause a current to flow in the cell, wherein the amount of such current is indicative of the value of the data stored in the cell. The memory device includes appropriate circuitry to sense the resulting cell current in order to determine the data stored therein, which is then provided to data bus terminals of the device for access to other devices in a system in which the memory device is employed.
Flash memory is a type of electronic memory media which can be rewritten and hold its content without power. Flash memory devices generally have life spans from 100K to 1MEG write cycles. Unlike dynamic random access memory (DRAM) and static random access memory (SRAM) memory chips, in which a single byte can be erased, flash memory is typically erased and written in fixed multi-bit blocks or sectors. Conventional flash memories are constructed in a cell structure wherein a single bit of information is stored in each flash memory cell. In such single bit memory architectures, each cell typically includes a MOS transistor structure having a source, a drain, and a channel in a substrate or P-well, as well as a stacked gate structure overlying the channel. The stacked gate may further include a thin gate dielectric layer (sometimes referred to as a tunnel oxide) formed on the surface of the P-well. The stacked gate also includes a polysilicon floating gate overlying the tunnel oxide and an interpoly dielectric layer overlying the floating gate. The interpoly dielectric layer is often a multilayer insulator such as an oxide-nitride-oxide (ONO) layer having two oxide layers sandwiching a nitride layer. Lastly, a polysilicon control gate overlies the interpoly dielectric layer.
FIG. 1
illustrates a typical NOR configuration
100
, wherein the control gate
110
is connected to a word line (e.g., WL
0
thru WL
3
) associated with a row of such cells
120
to form sectors of such cells. In addition, the drain regions
130
of the cells are connected together by a conductive bit line (e.g., BL
0
thru BL
3
). The channel of the cell conducts current between the source
140
and the drain
130
in accordance with an electric field developed in the channel by the stacked gate structure. In the NOR configuration, each drain terminal
130
of the transistors
120
within a single column is connected to the same bit line. In addition, each flash cell
120
associated with a given bit line has its stacked gate terminal
110
coupled to a different word line (e.g., WL
1
thru WL
4
), while all the flash cells in the array have their source terminals
140
coupled to a common source terminal (CS). In operation, individual flash cells
120
are addressed via the respective bit line and word line using peripheral decoder and control circuitry for programming (writing), reading or erasing functions.
Such a single bit stacked gate flash memory cell is programmed, for example, by applying a relatively high voltage to the control gate and connecting the source to ground and the drain to a predetermined potential above the source. A resulting high electric field across the tunnel oxide leads to a phenomena called “Towler-Nordheim” tunneling. During this process, electrons in the core cell channel region tunnel through the gate oxide into the floating gate and become trapped in the floating gate since the floating gate is surrounded by the interpoly dielectric and the tunnel oxide. As a result of the trapped electrons, the threshold voltage of the cell increases. This change in the threshold voltage (and thereby the channel conductance) of the cell created by the trapped electrons is what causes the cell to be programmed.
In order to erase a typical single bit stacked gate flash memory cell, a relatively high voltage is applied to the source, and the control gate is held at a negative potential, while the drain is allowed to float. Under these conditions, a strong electric field is developed across the tunnel oxide between the floating gate and the source. The electrons that are trapped in the floating gate flow toward and cluster at the portion of the floating gate overlying the source region and are extracted from the floating gate and into the source region by way of Fowler-Nordheim tunneling through the tunnel oxide. As the electrons are removed from the floating gate, the cell is erased.
For a read operation, a certain voltage bias is applied across the drain to source of the cell transistor. The drain of the cell is the bit line, which may be connected to the drains of other cells in a byte or word group. The voltage at the drain in conventional stacked gate memory cells is typically provided at between 0.5 and 1.0 volts in a read operation. A voltage is then applied to the gate (e.g., the word line) of the memory cell transistor in order to cause a current to flow from the drain to source. The read operation gate voltage is typically applied at a level between a programmed threshold voltage (V
T
) and an unprogrammed threshold voltage. The resulting current is measured, by which a determination is made as to the data value stored in the cell.
In addition to the NOR configuration, some prior art flash memories also use a “virtual ground” architecture, as shown in
FIG. 2. A
typical virtual ground architecture
200
comprises rows
240
of flash cells
210
with its stacked gate terminal
215
coupled to an associated word line (e.g., WL
0
thru WL
n
)
240
, and columns (
260
,
270
,
280
,
290
) of flash cell pairs (
210
&
230
) with a drain
235
of one transistor
230
coupled to an associated bit line (e.g., BL
0
thru BL
m
) and the source
220
of the adjacent transistor
210
coupled to the same bit line
270
. In addition, each sin
Chen Pau-Ling
Chung Michael S. C.
Hollmer Shane
Kurihara Kazuhiro
Le Binh Q.
Advanced Micro Devices , Inc.
Elms Richard
Eschweiler & Associates LLC
Phung Anh
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