DRAM cells with repressed floating gate memory, low tunnel...

Details DRAM cells with repressed floating gate memory, low tunnel... DRAM cells with repressed floating gate memory, low tunnel...

2001-08-30

2004-06-22

Elms, Richard (Department: 2824)

Static information storage and retrieval

Floating gate

Particular biasing

C365S149000, C365S185080, C365S185260

Reexamination Certificate

active

06754108

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates generally to integrated circuits, and in particular to DRAM cells with repressed floating gate memory, metal oxide tunnel interpoly insulators.
BACKGROUND OF THE INVENTION
An essential semiconductor device is semiconductor memory, such as a random access memory (RAM) device. A RAM device allows the user to execute both read and write operations on its memory cells. Typical examples of RAM devices include dynamic random access memory (DRAM) and static random access memory (SRAM).
DRAM is a specific category of RAM containing an array of individual memory cells, where each cell includes a capacitor for holding a charge and a transistor for accessing the charge held in the capacitor. The transistor is often referred to as the access transistor or the transfer device of the DRAM cell.
FIG. 1
illustrates a portion of a DRAM memory circuit containing two neighboring DRAM cells
100
. Each cell
100
contains a storage capacitor
140
and an access field effect transistor or transfer device
120
. For each cell, one side of the storage capacitor
140
is connected to a reference voltage (illustrated as a ground potential for convenience purposes). The other side of the storage capacitor
140
is connected to the drain of the transfer device
120
. The gate of the transfer device
120
is connected to a signal known in the art as a word line
180
. The source of the transfer device
120
is connected to a signal known in the art as a bit line
160
(also known in the art as a digit line). With the memory cell
100
components connected in this manner, it is apparent that the word line
180
controls access to the storage capacitor
140
by allowing or preventing the signal (representing a logic “0” or a logic “1”) carried on the bit line
160
to be written to or read from the storage capacitor
140
. Thus, each cell
100
contains one bit of data (i.e., a logic “0” or logic “1”).
In
FIG. 2
a DRAM circuit
240
is illustrated. The DRAM
240
contains a memory array
242
, row and column decoders
244
,
248
and a sense amplifier circuit
246
. The memory array
242
consists of a plurality of memory cells
200
(constructed as illustrated in
FIG. 1
) whose word lines
280
and bit lines
260
are commonly arranged into rows and columns, respectively. The bit lines
260
of the memory array
242
are connected to the sense amplifier circuit
246
, while its word lines
280
are connected to the row decoder
244
. Address and control signals are input on address/control lines
261
into the DRAM
240
and connected to the column decoder
248
, sense amplifier circuit
246
and row decoder
244
and are used to gain read and write access, among other things, to the memory array
242
.
The column decoder
248
is connected to the sense amplifier circuit
246
via control and column select signals on column select lines
262
. The sense amplifier circuit
246
receives input data destined for the memory array
242
and outputs data read from the memory array
242
over input/output (
1
/
0
) data lines
263
. Data is read from the cells of the memory array
242
by activating a word line
280
(via the row decoder
244
), which couples all of the memory cells corresponding to that word line to respective bit lines
260
, which define the columns of the array. One or more bit lines
260
are also activated. When a particular word line
280
and bit lines
260
are activated, the sense amplifier circuit
246
connected to a bit line column detects and amplifies the data bit transferred from the storage capacitor of the memory cell to its bit line
260
by measuring the potential difference between the activated bit line
260
and a reference line which may be an inactive bit line. The operation of DRAM sense amplifiers is described, for example, in U.S. Pat. Nos. 5,627,785; 5,280,205; and 5,042,011, all assigned to Micron Technology Inc., and incorporated by reference herein.
DRAM devices are the most cost effective high speed memory used with computers and computer systems. They last (nearly) indefinitely and are available in very high density. They are, however, limited in the longevity of their memory. DRAM devices require constant refreshing and lose all knowledge of their state (i.e., contents) once power to the device is removed. It is desirable to have a memory device, such as a DRAM memory device, with all of the positive features of DRAM devices, e.g., cost, size, speed, availability, etc., that retains its memory state when power is removed from the device.
A DRAM cell with a nonvolatile component would be very beneficial in numerous computer systems and computer applications. One application would be the saving and/or restoring of the state of a central processing unit (CPU) that is executing software instructions in a protected mode of operation, an example of which is disclosed in U.S. Pat. No. 5,497,494 to Combs et al., which is hereby incorporated by reference in its entirety. This application typically involves the use of memory separate from the main memory of the computer, typically referred to as shadow RAM, from which a BIOS program is executed and the CPU state is to be stored to and retrieved from. This, however, consumes valuable chip real estate.
This holds true for other computer systems that utilize shadow memory, such as, for example, the fault tolerant system disclosed in U.S. Pat. No. 5,619,642 to Nielson et al., which is hereby incorporated by reference in its entirety. In a fault tolerant system, a main memory contains data and error detection codes associated with each piece of data. A separate shadow memory is used to store data corresponding to the data stored in the main memory. If the system determines that accessed data from the main memory is erroneous, the corresponding data from the shadow memory is used and thus, faults in the main memory do not adversely effect the system (i.e., the system is fault tolerant). Again, memory separate from the main memory is required, which adds cost and adds to the size and complexity of the system.
There have been attempts to include shadow memory on DRAM and SRAM devices, such as the memory disclosed in U.S. Pat. No. 5,399,516 to Bergendahl et al. and U.S. Pat. No. 5,880,991 to Hsu et al. These devices, however, place individual DRAM and/or SRAM cells on the same substrate as separate nonvolatile memory cells. They do not use a single DRAM (or SRAM) cell having its own integral nonvolatile component. Instead, separate cells are used, which adds cost, size and complexity to the memory. There are many other uses which require such a separate non-volatile memory component such as the shadow memory described above.
One type of non-volatile memory includes Flash memory. Flash memories are another form of non-volatile memory. Flash memories have become widely accepted in a variety of applications ranging from personal computers, to digital cameras and wireless phones. Both INTEL and AMD have separately each produced about one billion integrated circuit chips in this technology.
The original EEPROM or EARPROM and flash memory devices described by Toshiba in 1984 used the interpoly dielectric insulator for erase. Various combinations of silicon oxide and silicon nitride were tried. However, the rough top surface of the polysilicon floating gate resulted in, poor quality interpoly oxides, sharp points, localized high electric fields, premature breakdown and reliability problems.
Widespread use of flash memories did not occur until the introduction of the ETOX cell by INTEL in 1988. This extremely simple cell and device structure resulted in high densities, high yield in production and low cost. This enabled the widespread use and application of flash memories anywhere a non-volatile memory function is required. However, in order to enable a reasonable write speed the ETOX cell uses channel hot electron injection, the erase operation which can be slower is achieved by Fowler-Nordhiem tunneling from the floating gate to the source. The large barriers to electron tunneli

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