Memory array addressing

Memory array architecture for multi-data rate operation

Memory array decoder

Memory array decoder

Memory array decoder

Memory array having a plurality of address partitions

Memory array leakage reduction circuit and method

Memory array leakage reduction circuit and method

Memory array leakage reduction circuit and method

Memory array using selective device activation

Memory array using selective device activation

Memory array with a simultaneous read or simultaneous write port

Memory array with common word line

Memory array with dual wordline operation

Memory array with multiple read ports

Memory array with staged output

Memory array with staged output

Memory bank structure

Memory block address determination circuit

Memory block reallocation in a flash memory device