Memory array architecture for multi-data rate operation

Details Memory array architecture for multi-data rate operation Memory array architecture for multi-data rate operation

1998-11-18

2000-07-25

Nelms, David

Static information storage and retrieval

Addressing

Plural blocks or banks

36518904, G11C 800

Patent

active

060943963

ABSTRACT:
A memory array architecture (which can be used to implement a memory device and other circuits having an embedded memory array) supports multi-data rate operation. The memory device includes at least one memory array and at least one sense amplifier arrays. Each memory array is partitioned into a number of substantially similar segments. Each segment is associated with at least one local I/O lines. Each local I/O line has a length that is a portion of a length of the memory array. By partitioning the memory array, the supporting circuitry (e.g., the sense amplifier array), and the local I/O lines into segments, access of multiple data bits can be achieved without having to incur a significant "die penalty."

REFERENCES:
patent: 4733376 (1988-03-01), Ogawa
patent: 5617555 (1997-04-01), Patel
patent: 5930194 (1999-07-01), Yamagata et al.
patent: 5940329 (1999-08-01), Seitsinger et al.

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