Memory array having a plurality of address partitions

Details Memory array having a plurality of address partitions Memory array having a plurality of address partitions

1994-01-25

1994-10-25

LaRoche, Eugene R.

Static information storage and retrieval

Addressing

Plural blocks or banks

3652385, 36518905, 365220, 365185, 36523006, 365900, G11C 800

Patent

active

053595718

ABSTRACT:
Non-volatile semiconductor memory integrated circuits which partition a main memory array into sub-arrays. Address lines of the main memory array are also partitioned into four groups. The first group and the second group are dedicated for the addressing of the sub-arrays. Each of the sub-arrays can be addressed by a simultaneous energization of a pair of address lines selected from the first and the second group. The third group and the fourth group are used for the addressing for individual memory cells in the sub-arrays. The simultaneous energization of a pair of address lines selected from the third and the fourth group can address any of the memory cells within a selected sub-array. The memory circuits of the present invention are applicable for memory cells with four terminals. In a first embodiment of the invention, the memory circuit is a one-bit wide circuit. In a second and a third embodiment of the invention, the memory circuits are designed as multi-bit-wide circuits whereby data can be programmed parallely. Moreover, in the third embodiment, storage register circuits are implemented, such that during programming, data are cumulatively loaded into the register circuits within a time period, and are simultaneously programmed into the main array within another time period. The programming and the cumulative data loading steps are executed concurrently, resulting in no idle time being wasted. As a consequence, programming can be as fast as reading for memory circuit of the third embodiment of the invention.

REFERENCES:
patent: 4099196 (1978-07-01), Simko
patent: 4334292 (1982-06-01), Kotecha
patent: 4511996 (1985-04-01), Jacobs
patent: 4780750 (1988-10-01), Nolan et al.
patent: 5280446 (1994-01-01), Ma et al.
patent: 5303187 (1994-04-01), Yu

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