Static information storage and retrieval – Addressing
Patent
1981-06-04
1984-01-31
Stellar, George G.
Static information storage and retrieval
Addressing
G11C 800
Patent
active
044293747
ABSTRACT:
The address decoder for one axis comprises NAND circuits while the address decoder for the other axis comprises NOR circuits. A semiconductor memory circuit device comprises at least first and second decoder circuits. The first decoder circuit is so constructed as to receive at least partial address signals among address signals of a plurality of bits and to provide decoded signals of the partial address signals as intermediate signals. The second decoder circuit is so constructed as to receive the intermediate signals, to thereby provide signals for selecting from among a plurality of memory circuits a memory circuit determined by the address signals of the plurality of bits. Thus, the semiconductor memory circuit device is allowed to operate at a high speed. A semiconductor substrate on which the semiconductor memory circuit device is formed can also be made comparatively small.
REFERENCES:
patent: 4094012 (1978-06-01), Perlegos et al.
patent: 4103349 (1978-07-01), Marmet
patent: 4104735 (1978-08-01), Hofmann et al.
patent: 4194130 (1980-03-01), Moench
patent: 4264828 (1981-04-01), Perlegos et al.
patent: 4344005 (1982-08-01), Stewart
Firmenprospekt "Announcing, Mosteks," MK 4027 pp. 1-4.
Siemens-Forschunk und Entwicklung, Beright, NR. 4, 1975, pp. 197-202 "A 4096-Bit MOS Memory Device with Single-Transistor Cells" Heibing et al.
Hitachi , Ltd.
Stellar George G.
LandOfFree
Memory array addressing does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Memory array addressing, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Memory array addressing will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2349141