Static information storage and retrieval – Addressing – Plural blocks or banks
Reexamination Certificate
2001-02-15
2004-03-30
Ho, Hoai (Department: 2818)
Static information storage and retrieval
Addressing
Plural blocks or banks
C365S149000, C365S230060
Reexamination Certificate
active
06714476
ABSTRACT:
FIELD OF THE INVENTION
This invention relates to the field of integrated circuit (IC) design. Specifically, it relates to a dynamic random access memory (DRAM) array interchangeable between single-cell and twin-cell array operation.
BACKGROUND OF THE INVENTION
Each memory cell in a dual-port static random access memory (SRAM) chip is a buffer or flip-flop, and data is retained as long as power is maintained to the chip. SRAMs are realized with a bipolar technology, such as TTL, ECL, or I
2
L or with MOS technology, such as NMOS or CMOS. Bipolar SRAMs are relatively fast, having access times of 10 to 100 nsec. Power dissipation is also high, typically, 0.1 to 1.0 mW/bit. By contrast, MOS RAM access time is typically 100 nsec and power dissipation is 25 &mgr;W/bit. The combination of high circuit density, low power dissipation, and reasonable access time has led to the dominance of MOS technology in the manufacture of RAM. Hence, dual-port SRAMs having high-speed buffers are widely used in devices and equipment necessitating high-speed and high performance, such as microprocessors, communication networks, facsimile machines, modems, etc.
Since the memory cells of SRAMs take up a relatively large surface area on a single integrated (IC) chip, IC design engineers, in an effort to increase the number of memory cells on the IC chip, i.e., high density, and make the chip smaller, have focused on improving dynamic RAM (DRAM) chips to make them suitable for high-speed, high performance devices and equipment. Currently, the ultimate in achieving high-density and compactness, is a DRAM chip capable of storing data in the single-cell array format where each memory cell uses a capacitor to store a charge and one transistor to gate it to sense amplifier circuits.
Nonetheless, the single-cell storage configuration does not have a low-operating voltage, does not consume low-power, does not retain data for long periods of time, and is not suitable for high-speed, high-performance applications, as compared to a DRAM chip capable of storing data in the twin-cell array format. Accordingly, it is envisioned to provide a DRAM array capable of storing data in both the single-cell and twin-cell array format, where the DRAM array is interchangeable between single-cell and twin-cell array operation.
SUMMARY
An aspect of the present invention is to provide a DRAM array capable of storing data in both the single-cell and twin-cell array format, where the DRAM array is interchangeable between single-cell and twin-cell array operation.
Another aspect of the present invention is to provide a DRAM array capable of storing data in both the single-cell and twin-cell array format, where the operating voltage of the DRAM array is reduced when the data is stored in the twin-cell array format.
Further, another aspect of the present invention is to provide a DRAM array capable of storing data in both the single-cell and twin-cell array format, where the refresh period of the DRAM array is extended when the DRAM array is operated as a twin-cell array, as compared to when the DRAM array is operated as a single-cell array.
Further still, another aspect of the present invention is to provide a DRAM array capable of storing data in both the single-cell and twin-cell array format, where data can be converted from the single-cell array format to the twin-cell array format, and vice versa.
Finally, another aspect of the present invention is to provide a DRAM array capable of storing data in both the single-cell and twin-cell array format, where, during one operating mode, e.g., an active mode, the DRAM array is operated as a single-cell array, while, during another operating mode, e.g., a low-power mode, the DRAM array is operated as a twin-cell array.
Accordingly, in an embodiment of the present invention, a DRAM array is provided capable of being interchanged between single-cell and twin-cell array operation for storing data in the single-cell or the twin-cell array format, respectively. Preferably, the DRAM array is operated in the single-cell array format during one operating mode and the DRAM array is operated in the twin-cell array format during another operating mode.
Wordline decoding circuitry is included for interchanging the DRAM array between single-cell and twin-cell array operation. The wordline decoding circuitry includes a pre-decoder circuit for receiving a control signal and outputting logic outputs to wordline activation circuitry. The wordline activation circuitry then activates at least one wordline traversing the array for interchanging memory cells within the DRAM array between single-cell array operation and twin-cell array operation.
Methods are also provided for converting data stored within the DRAM array from the single-cell to the twin-cell array format, and vice versa. A method for converting data from a single-cell array format to a twin-cell array format includes the steps of activating a first wordline traversing a data array; reading data stored within a first group of cells of the data array which are coupled to the first wordline to corresponding sense amplifiers; and activating at least a second wordline traversing the data array to write the data from the corresponding sense amplifiers to a second group of cells of the data array.
A method for converting data from a twin-cell array format to a single-cell array format includes the steps of activating at least a first wordline traversing a data array; reading data stored within a first group of cells of the data array which are coupled to the at least first wordline to corresponding sense amplifiers; and activating a second wordline traversing the data array to write data from the corresponding sense amplifiers to a second group of cells of the data array.
REFERENCES:
patent: 5862095 (1999-01-01), Takahashi et al.
patent: 6272054 (2001-08-01), Barth et al.
patent: 6344990 (2002-02-01), Matsumiya et al.
patent: 6449204 (2002-09-01), Arimoto et al.
Assaderaghi Fariborz
Hsu Louis L.
Joshi Rajiv V.
Dilworth & Barrese LLP
Ho Hoai
IBM Corporation
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