Memory array leakage reduction circuit and method

Details Memory array leakage reduction circuit and method Memory array leakage reduction circuit and method

2008-03-18

2008-03-18

Elms, Richard T. (Department: 2824)

Static information storage and retrieval

Addressing

Particular decoder or driver circuit

C365S226000, C365S227000, C365S228000, C365S229000

Reexamination Certificate

active

07345947

ABSTRACT:
Embodiments of the invention provide techniques for reducing standby power consumption due to leakage currents in memory circuits. In some embodiments, systems are provided with one or more processors having) bit cells coupled to a word-line node and to a virtual ground node. The word-line node is to be at an active word-line voltage when the row is active and an inactive word-line voltage when the row is inactive. The virtual ground node is to be at an operational ground voltage when the memory array is enabled and at an elevated voltage when the memory array is in a standby mode. There is also a word-line driver circuit coupled to the bit cells through the word-line and virtual ground nodes. The current leakage in the bit cells and word-line driver circuit is reduced during the standby mode when the virtual ground node is at the elevated voltage.

REFERENCES:
patent: 6515513 (2003-02-01), Ye et al.
patent: 6862207 (2005-03-01), Wei et al.

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