Memory block address determination circuit

Details Memory block address determination circuit Memory block address determination circuit

1989-02-21

1991-01-08

Popek, Joseph A.

Static information storage and retrieval

Addressing

36523006, 36518907, 36518908, 365239, G11C 700, G11C 800, G11C 11407

Patent

active

049842137

ABSTRACT:
An adder and a comparator form portions of a modular memory address block determination circuit. The starting address of the first block and the enable signal of the first block are added to produce the starting address of the second block. This procedure is repeated for each block. The determined starting address for each block is compared with the requested memory address and, unless the block is utilized or disabled, if equal a signal indicates the match. The circuit is used on a circuit board which emulates three conventionally separate memory circuit boards. The registers for each emulated board are provided and appropriate bus signals are developed.

REFERENCES:
patent: 4280199 (1981-07-01), Osakabe et al.
patent: 4303993 (1981-12-01), Panepinto, Jr. et al.
patent: 4354258 (1982-10-01), Sato
patent: 4458357 (1984-07-01), Weymouth et al.
patent: 4811297 (1989-03-01), Ogawa
IBM Corp., Personal System/2 Model 80 Technical Reference, First Edition, Apr. 1987, pp. 2-34 to 2-43.

Affiliated with

Also associated with

Rating

Memory block address determination circuit does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Memory block address determination circuit, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Memory block address determination circuit will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-940950