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Negative resistance memory cell and method

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
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NFET and PFET devices and methods of fabricating same

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
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NFET and PFET devices and methods of fabricating same

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
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NFETs using gate induced stress modulation

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
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NH3/N2-plasma treatment for reduced nickel silicide bridging

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
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NiSi metal gate stacks using a boron-trap

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
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Nitridation process for fabricating an ONO floating-gate...

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
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Nitridation process with peripheral region protection

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
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Nitride barrier layer for protection of ONO structure from...

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
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Nitride cap formation in a DRAM trench capacitor

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
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Nitride deposition wafer to wafer native oxide uniformity...

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
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Nitride disposable spacer to reduce mask count in CMOS transisto

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
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Nitride disposable spacer to reduce mask count in CMOS...

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
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Nitride encapsulated thin film transistor fabrication technique

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – On insulating substrate or layer
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Nitride layer on a gate stack

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
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Nitride overhang structures for the silicidation of transistor e

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
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Nitride plug to reduce gate edge lifting

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
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Nitride read only memory cell

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
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Nitride read only memory device with buried diffusion...

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
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Nitride read only memory device with buried diffusion...

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
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