Global column select structure for accessing a memory
Global column select structure for accessing a memory
Graded composition gate insulators to reduce tunneling...
Graded layer for use in semiconductor circuits and method...
Graded LDD implant process for sub-half-micron MOS devices
Graded LDD implant process for sub-half-micron MOS devices
Graded LDD implant process for sub-half-micron MOS devices
Graphene-based transistor
Grooved planar DRAM transfer device using buried pocket
Growth enhancement of hemispherical grain silicon on a doped pol
Growth technique for low noise high electron mobility...
Guard mesh for noise isolation in highly integrated circuits
Guard ring structures for high voltage CMOS/low voltage CMOS...