Graded LDD implant process for sub-half-micron MOS devices

Details Graded LDD implant process for sub-half-micron MOS devices Graded LDD implant process for sub-half-micron MOS devices

2005-02-22

2005-02-22

Chen, Jack (Department: 2813)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S305000, C438S307000, C438S595000

Reexamination Certificate

active

06858507

ABSTRACT:
A process for grading the junctions of a lightly doped drain (LDD) N-channel MOSFET by performing a low dosage phosphorous implant after low and high dosage arsenic implants have been performed during the creation of the N-LDD regions and N+ source and drain electrodes. The phosphorous implant is driven to diffuse across both the electrode/LDD junctions and the LDD/channel junctions.

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