Graded LDD implant process for sub-half-micron MOS devices

Details Graded LDD implant process for sub-half-micron MOS devices Graded LDD implant process for sub-half-micron MOS devices

1997-03-17

2000-12-12

Booth, Richard

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

438529, H01L 2184

Patent

active

061598135

ABSTRACT:
A process for grading the junctions of a lightly doped drain (LDD) N-channel MOSFET by performing a low dosage phosphorous implant after low and high dosage arsenic implants have been performed during the creation of the N- LDD regions and N+ source and drain electrodes. The phosphorous implant is driven to diffuse across both the electrode/LDD junctions and the LDD/channel junctions.

REFERENCES:
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patent: 5217910 (1993-06-01), Shimizu et al.
patent: 5716862 (1998-02-01), Ahmad et al.
patent: 5770505 (1998-06-01), Om et al.
#C.Y. Wei, et al., "Reliability and Performance of Submicron LDD NMOSFET's with buried-As-n-Impurity Profies", IEDM Tech. Dig., pp. 246-249 (1985).
#"Buried and Graded/Buried LDD Structures for Improved Hot-Electron Reliability", IEEE Electron Device Lett., vol. EDL-7, pp. 6 (Jun. 1986).

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