Global column select structure for accessing a memory

Details Global column select structure for accessing a memory Global column select structure for accessing a memory

2002-08-05

2004-08-17

Dang, Phuc T. (Department: 2818)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S405000, C438S453000

Reexamination Certificate

active

06777290

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to integrated circuit memory devices, and, more particularly, to a global column select structure for accessing a memory, such as a dynamic random access memory (DRAM), for example.
2. Description of the Related Art
Modem integrated circuit memory devices generally include high density memory arrays on an integrated circuit chip. The array contains many memory cells, each of which stores a bit of data. In many memory devices, such as dynamic random access memories (DRAMs), for example, each of the memory cells stores an electrical charge, where the value of the electrical charge is indicative of the logical bit value stored in the cell. The absence of an electrical charge in the memory cell may indicate a logical “zero;” whereas, the presence of an electrical charge in the memory cell may indicate a logical “one.”
The numerous memory cells in an integrated circuit memory device are typically arranged in an array having a number of intersecting rows and columns. One memory cell is normally associated with each intersection of a row and a column. Word lines, which correspond to rows in the array, are used to access the memory cells connected to that word line. Bit lines, which correspond to columns in the array, are used to interconnect memory cells to sense amplifiers where the presence or absence of an electrical charge in the memory cell can be detected. Row decoders and column decoders activate a selected word line and a selected bit line to access a particular memory cell as designated by an address input to the memory device.
Typically, the various columns of the memory array are grouped into sub arrays. Data within these columns is retrieved by either a column select (CS) bit line or a global column select (GCS) bit line that is routed from a periphery of the integrated circuit chip to the memory array. Generally, the CS bit line is used to address a particular sense amplifier to select from a column of data within a “local” sub array. The GCS bit line, on the other hand, is used to “globally” select from particular columns of data from the sub arrays. Typically, the CS bit line is routed from the periphery of the integrated circuit chip to the memory array through an intermediate layer that separates an upper data storage (e.g., capacitive) layer and a lower logic layer that forms the memory array. The GCS bit line is typically routed above the data storage layer (i.e., above the memory array) between the periphery of the integrated circuit chip and the memory array.
It is generally desired in device designs incorporating PCRAM operation, for example, to have the area over the data storage layer (i.e., the memory array) free of any patterning to allow for cell definition. Because the GCS bit line is typically routed over the memory array, the area over the array is not substantially free, which may make PCRAM operation difficult (i.e., it is desirable to form PCRAM memory cell materials as a continuous sheet). Additionally, because the height of the data storage layer is typically on an order of three times the height of the logic layer, routing the GCS bit line over the data storage layer yields a very deep via that must be etched in the integrated circuit chip to route the GCS line down to the substrate of the chip. For example, the via could be as much as 3 microns deep, which is highly undesirable when 0.1-0.15 micron design constraints are typically contemplated.
The present invention is directed to overcoming, or at least reducing the effects of, one or more of the problems set forth above.
SUMMARY OF THE INVENTION
In one aspect of the present invention, a method is provided. The method includes forming a first conductive layer between a data storage layer and a control layer of a memory. A second conductive layer is formed beneath the first conductive layer. The first and second conductive layers provide addressing and data retrieval between the memory and a periphery of an integrated circuit chip.
In another aspect of the present invention, a method for forming conductive layers in an integrated circuit chip is provided. The integrated circuit chip comprises a periphery portion and a memory portion, the memory portion including a capacitive layer and a logic layer formed underneath the capacitive layer and separated therefrom by an intermediate layer. The method comprises forming a first conductive layer within the intermediate layer to communicatively couple the periphery and memory portions of the integrated circuit chip, and forming a second conductive layer within the intermediate layer to communicatively couple the periphery and memory portions of the integrated circuit chip. The first and second conductive layers provide addressing and data retrieval between the memory portion and the periphery portion.
In another aspect of the present invention, an integrated circuit chip is provided. The chip comprises a periphery portion for generating addressing information and a memory portion for storing data in a plurality of memory cells forming an array. The memory portion comprises a capacitive layer, a logic layer residing below the capacitive layer, and an intermediate layer formed between the capacitive layer and the logic layer. The intermediate layer includes first and second conductive layers to communicatively couple the periphery and memory portions. The first and second conductive layers provide the addressing information generated from the periphery portion to the array for retrieving data therefrom.
In another aspect of the present invention, a system is provided. The system comprises a processor and a memory for storing data in a plurality of memory cells forming an array. The memory comprises a data storage layer, a control layer residing beneath the data storage layer, and first and second conductive layers formed between the data storage layer and the control layer to communicatively couple a chip periphery and the memory. The first and second conductive layers providing addressing information generated by the chip periphery to the array for retrieving data therefrom.
In another aspect of the present invention, a computer system is provided. The computer system comprises a processor and a memory. The memory comprises a capacitive layer, a logic layer residing beneath the capacitive layer, and column select (CS) and global column select (GCS) bit lines formed between the capacitive and logic layers to communicatively couple the memory to a chip periphery. The CS and GCS bit lines provide addressing information generated by the chip periphery to an array of the memory for retrieving data therefrom.
In another aspect of the present invention, a memory device is provided for storing data in a plurality of memory cells forming an array. The memory device comprises a data storage layer, a control layer residing beneath the data storage layer, and first and second bit lines formed between the data storage and control layers to communicatively couple the memory device to a periphery of a chip, the first and second bit lines providing addressing information generated from the periphery of the chip to the array for retrieving data therefrom.
In another aspect of the present invention, a system board is provided. The system board comprises a periphery component and a memory component. The memory component includes a capacitive layer, a logic layer residing beneath the capacitive layer, and an intermediate layer formed between the capacitive layer and the logic layer. The intermediate layer includes first and second conductive layers to communicatively couple the periphery and memory components. The first and second conductive layers provide addressing information generated by the periphery component to an array of the memory component for retrieving data therefrom.


REFERENCES:
patent: 5247480 (1993-09-01), Itoh et al.

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