Master/slave method for a ZQ-circuitry in multiple die devices
Mechanism for automatically enabling and disabling clock signals
Memory clock slowdown synthesis circuit
Memory device initialization
Memory reset apparatus
Meta-hardened flip-flop
Metastable protected latch
Metastableproof flip-flop
Method and an apparatus to generate static logic level output
Method and apparatus for a configurable latch
Method and apparatus for enabling a stand alone integrated...
Method and apparatus for glitch protection for input buffers...
Method and apparatus for latching a clocked data signal
Method and apparatus for latching data within a digital system
Method and apparatus for providing noise immunity for a...
Method and apparatus for reducing charge sharing and the...
Method and apparatus for reducing the vulnerability of...
Method and apparatus for reducing the vulnerability of...
Method and apparatus for test mode entry during power up
Method and apparatus to delay signal latching