Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Particular stable state circuit
Reexamination Certificate
2001-05-03
2003-01-14
Wells, Kenneth B. (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Signal converting, shaping, or generating
Particular stable state circuit
C327S212000
Reexamination Certificate
active
06507228
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to clocked latches in electronic circuitry, and more particularly to such latches which are suitable for application with a high frequency clock.
2. Related Art
For high-speed communications systems, true/complement edge triggered latches are used extensively for sampling both data and clock signals. True/complement level sensitive latches are also used. To maximize data rate, both latch speed and skew between true and complement output signals must be minimal. Existing static latch designs show significant time differences between clock-to-true-output and clock-to-complement-output, since typically one output drives the other output. At very high speeds, the propagation delay through an inverter can be an appreciable portion of the cycle time or baud interval, and the skew between a signal and its complement can be increased or accumulated in subsequent stages. U.S. Pat. No. 5,825,225 shows a technique for boosting the speed of a latch, but it does not teach differential outputs with low skew. U.S. Pat. No. 5,625,308 shows a differential latch which combines a latch circuit with an analog differential amplifier, but it does not provide full rail to rail swing due to analog nature of the amplifier with biased active load devices which drop the signal down from Vdd.
FIG. 5 illustrates a prior art static latch 500. Weste and Eshraghian, Principles of CMOS VLSI Design, second edition, FIG. 5.55 b, page 328, 1993. In an initial condition for this latch 500, data is low, as is output node Q, and output node Q_bar is high. With data high, upon clock going high node Q_bar is immediately pulled low through the FET's that receive the data and clock signals; however, node Q is not immediately driven high. Instead, node Q is driven high only after node Q_BAR is pulled low and propagates through the cross-coupled inverter element, i.e., memory, between nodes Q and Q_bar. Likewise, with data low, upon clock going high node Q is immediately pulled low and node Q_bar is pulled high after propagation through the memory. This skew is problematic.
Dynamic latches suffer from the same skew problems as static latches and are difficult to interface with surrounding static circuits. Therefore a need exists for improvements in a fast, latch with low skew between complementary outputs.
SUMMARY
The foregoing need is addressed in the following invention, according to which, in one form, a latch includes a memory having two nodes and pulldown circuitry coupled to the nodes for pulling one of them down to a low state responsive to a data signal. The pulldown circuitry has gating circuitry for timing the pulling down responsive to a pulldown circuitry clock signal. The latch also has pull up circuitry, which has a first pull up circuitry section coupled to one of the memory nodes for pulling the node up to a high state responsive to a pull up circuitry data signal. The first pull up circuitry section includes second gating circuitry for timing the pulling up responsive to a pull up circuitry clock signal. It is an advantage that the first pull up circuitry section more quickly pulls up the node, so that one memory node is pulled down and the other one is pulled up at more nearly the same time.
In another aspect, the pull up circuitry has a second pull up circuitry section for pulling up the other one of the memory nodes responsive to the pull up circuitry clock signal and a complement of the pull up circuitry data signal. It is an advantage of including the second pull up circuitry section that the first and second memory nodes will each be pulled up, in respective instances, and that the pull up times will more nearly match the times for pulling down the complementary node in each instance.
In a further aspect, the latch has delay circuitry operable to assert and deassert a delay signal, responsive to a delay circuitry clock signal and to a delay interval. The pulling up and pulling down is enabled during the delay interval. After the delay interval the isolation circuitry of the latch isolates the memory nodes from pull up and pulldown voltages until the delay circuitry responds to a new state of the delay circuitry clock signal, at which time the gating circuitry isolates the nodes until the next change in state of the gating circuitry clock. It is an advantage to include the delay and isolation circuitry in the latch so that the state of the data signal is captured during a narrow and controllable window of time. In contrast, in a latch such as latch 500 of FIG. 5, the output of the latch 500 is responsive to changes in the data signal any time the clock signal is high.
In a still further aspect, the delay interval is longer in one instance than in another, depending on the state of the delay circuitry clock signal. This is advantageous since the longer delay permits the memory nodes to be more fully driven to their respective states before the isolation circuitry isolates the memory.
Other objects and advantages of the invention will become apparent upon reading the following detailed description and upon reference to the accompanying drawings.
REFERENCES:
patent: 5508648 (1996-04-01), Banik
patent: 5625308 (1997-04-01), Matsumoto et al.
patent: 5650735 (1997-07-01), Ko
patent: 5751649 (1998-05-01), Kornachuk et al.
patent: 5764089 (1998-06-01), Partovi et al.
patent: 5825225 (1998-10-01), Sugisawa et al.
patent: 6084455 (2000-07-01), Matson
patent: 6275071 (2001-08-01), Ye et al.
patent: 6292407 (2001-09-01), Porter et al.
Weste and Eshraghian, “Principles of CMOS VLSI Design”, 2nd edition, Fig 5.55b, p. 328, 1993.
Weste and Eshraghian, “Principles of CMOS VLSI Design”, 2nd edition, Fig 5.58, p. 331, 1993.
Boerstler David William
Takahashi Osamu
Cox Cassandra
England Anthony V. S.
Salys Casimer K.
Wells Kenneth B.
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