Method and apparatus for test mode entry during power up

Details Method and apparatus for test mode entry during power up Method and apparatus for test mode entry during power up

1996-09-12

1997-12-30

Callahan, Timothy P.

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Particular stable state circuit

327143, H03K 1722

Patent

active

057035121

ABSTRACT:
An integrated circuit includes test circuitry and test mode enable circuitry. During power-up, an over-voltage on a package pin of the integrated circuit can initiate a test mode. The test mode enable signal may be latched into its activity state by a signal provided on a second package pin. Thereafter, the first and second package pins may be used in the normal voltage range during the test operations.

REFERENCES:
patent: 4716322 (1987-12-01), D'Arrigo et al.
patent: 4886984 (1989-12-01), Nakaoka
patent: 5159206 (1992-10-01), Tsay et al.
patent: 5469099 (1995-11-01), Konishi

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