Memory reset apparatus

Details Memory reset apparatus Memory reset apparatus

2008-01-08

2009-11-10

Donovan, Lincoln (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Particular stable state circuit

C711S166000, C713S001000

Reexamination Certificate

active

07616039

ABSTRACT:
A memory reset apparatus including a first inverse circuit, a logic circuit, and a plurality of second inverse circuits is provided. The first inverse circuit receives a control signal generated by a north bridge and generates a first signal, in which the control signal controls reset of a plurality of memories. The logic circuit performs a logic operation of the first signal and an indicating signal and generates a second signal, in which the indicating signal indicates each component of a computer system completely powered on. The plurality of second inverse circuits is respectively coupled between the logic circuit and the memories. The second inverse circuits inverse the second signal and respectively generate a plurality of reset signals to the memories, so as to reset the memories.

REFERENCES:
patent: 6147542 (2000-11-01), Yaklin
patent: 6172936 (2001-01-01), Kitazaki
patent: 2007/0005952 (2007-01-01), Ho
patent: 270818 (2007-01-01), None

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