Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Particular stable state circuit
Reexamination Certificate
2000-03-13
2002-04-23
Cunningham, Terry D. (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Signal converting, shaping, or generating
Particular stable state circuit
C327S566000
Reexamination Certificate
active
06377097
ABSTRACT:
FIELD OF THE INVENTION
This invention relates generally to the field of semiconductor electronics. More particularly, this invention relates to making semiconductor electronics less vulnerable to radiation. Even more particularly, this invention relates to reducing the vulnerability of latches to single event upsets.
BACKGROUND OF THE INVENTION
When an particle with sufficient energy passes through a semiconductor it creates electron-hole pairs along its path. If the electron-hole pairs occur in a sensitive region, such as the drains of N-type or P-type FETs, the electron-hole pairs generate a current that temporarily changes the voltage at the drain node in an occurrence called a “glitch.” After a “recovery time,” the electrons and holes generated by the passage of the particle are absorbed or carried away and the drain voltage returns to normal.
A glitch can be particularly disruptive to memory cells or latch circuits. Such circuits have feedback paths through which a glitch can be reinforced and stabilized before the node's recovery time has elapsed causing the node to stabilize in the glitch-induced state. Such an event is referred to as a single event upset or “SEU.”
The latch circuit illustrated in
FIG. 1
is an example of a circuit that is susceptible to an SEU. A Data signal is applied to Data terminal
102
, which is coupled to the gates of P-type FET
104
and N-type FET
106
. These FETs perform a buffer function isolating the input Data signal from the loads required to operate the flip flop. If the input Data signal is high (as that term is understood by persons of ordinary skill in the art) then FET
106
turns on pulling node
108
low. If Data is low, FET
104
turns on pulling node
110
high.
The signal GB (gate bar) determines whether the flip flop holds its current state (GB high) or tracks the input Data signal (GB low). FET's
112
,
114
,
116
and
118
are gating logic that configure the flip flop for storage (holding current state) or tracking, and, FET's
120
,
122
,
124
and
126
are a pair of inverters (
128
and
130
, respectively) that accomplish the storage function.
With GB low, FET's
112
and
114
are “on”, completing the path between the buffered Data nodes
108
and
110
and the coupling node
126
. FET's
116
and
118
are “off”, interrupting the feedback path that re-inforces storage. In this condition the state of the flip flop tracks the input Data signal until GB goes high again.
When the GB signal is high, the Q and QB outputs are maintained by a feedback loop composed of FETs
116
and
118
(which form a transmission gate), inverter
128
and inverter
130
.
To illustrate the effect of a glitch on this circuit, suppose that the signal applied to the GB terminal is high, the Q output is high and the QB output is low. This means that nodes
132
,
134
,
136
and
138
are low and node
140
is high. Note that nodes
132
and
134
are the same physical node and that nodes
136
and
138
are the same physical node. If a glitch occurs at, for example, node
134
causing it to be driven high, inverter
130
will drive node
140
low. The signal at node
140
will be fed back to the input of inverter
128
which will drive nodes
136
and
138
high. If the feedback occurs before node
130
has a chance to recover from the glitch, node
134
will be driven high and an SEU will have occurred.
Glitches can occur in the latch, as discussed above, or they can be generated in logic outside the latch and propagate into the latch through a control line, for example, and cause an SEU.
Existing approaches to making circuits SEU-resistant include inserting resistors, capacitors or delay elements, such as inverters, in the feedback loop to slow the response of the loop to the glitch and thereby absorb it. Other approaches use redundancy and cross-coupled elements.
SUMMARY OF THE INVENTION
In general, in one aspect, the invention features a delay circuit comprising a first network having an input and an output node, a second network having an input and an output, the input of the second network being coupled to the output node of the first network. The first network and the second network are configured such that: a glitch at the input to the first network having a length of approximately one-half of a standard glitch time or less does not cause the voltage at the output of the second network to cross a threshold, a glitch at the input to the first network having a length of between approximately one-half and two standard glitch times causes the voltage at the output of the second network to cross the threshold for less than the length of the glitch, and a glitch at the input to the first network having a length of greater than approximately two standard glitch times causes the voltage at the output of the second network to cross the threshold for approximately the time of the glitch.
Implementations of the invention may include one or more of the following. The network may comprise a P-type FET and an N-type FET. The gates of the two FETs may be coupled together and the drains of the two FETs may be coupled together. The source of the P-type FET may be coupled to the power source and the source of the N-type FET being coupled to ground. The channel of at least one of the FETs may be non-linear. The channel of the at least one of the FETs may include agog. The jog may be a right angle. The second network may be an inverter. The voltage at the output of the second network may cross the threshold after a delay relative to the arrival of the glitch at the input to the first network. The delay may be determined by characteristics of the first network and characteristics of the second network.
In general, in another aspect, the invention features an SEU-resistant circuit comprising a gate having an input and an output and a feedback path from the output of the gate to the input of the gate. The feedback path comprises two or more delay elements. The gate and the two or more delay elements are configured to absorb a standard glitch at the input to the gate before it propagates through the feedback path to the input of the gate. The delay is spread among the gate and the two or more delay elements.
Implementations of the invention may include one or more of the following. The delay may be substantially evenly spread among the gate and the two or more delay elements. The delay elements may comprise balanced gates. The feedback path may further comprise a driver gate. The delay elements may comprise inverters. The number of delay elements may be even.
In general, in another aspect, the invention features an SEU-resistant circuit having a first state and a second state. The SEU-resistant circuit comprises a first flip-flop having a first state and a second state. The first flip-flop is configured to change state upon application of a signal to a first flip-flop signal input. The SEU-resistant circuit also comprises a second flip-flop having a first state and a second state equivalent to the first state and the second state of the first flip-flop. The second flip-flop is configured to change state upon application of a signal to a second flip-flop signal input. The first flip-flop is coupled to the second flip-flop such that the SEU-resistant circuit does not change from its first state to its second state unless the state of the first flip-flop agrees with the state of the second flip-flop. The SEU-resistant circuit includes an input to receive a signal to cause the SEU-resistant circuit to change states when the signal changes states. The input is coupled to the first flip-flop signal input. The input is coupled to the second flip-flop signal input through a delay circuit. The input is for one of a clock, reset or preset signal.
Implementations of the invention may include one or more of the following. The delay circuit may be non-inverting. The delay circuit may have a delay greater than the maximum expected glitch time.
In general, in another aspect, the invention features a transition NAND gate comprising two or more inp
Barr Hardie R.
Cunningham Terry D.
Dinh Paul
The United States of America as represented by the Administrator
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