Mechanism for automatically enabling and disabling clock signals

Details Mechanism for automatically enabling and disabling clock signals Mechanism for automatically enabling and disabling clock signals

1996-05-10

1998-05-19

Wambach, Margaret Rose

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Particular stable state circuit

327142, 327291, 327365, 327594, 364707, 39575006, H03K 1722, H03K 1728, G06F 110

Patent

active

057540691

ABSTRACT:
A mechanism for automatically enabling and disabling clock signals includes a driver for providing a clock signal as an output, a gate coupled to the driver, and a sensing circuit coupled to both the output of the driver and to the gate. The sensing circuit provides a signal to the gate responsive to the output being in a first state. The gate then prevents the driver from driving the clock signal responsive to the signal from the sensing circuit. In one embodiment, a generator is coupled to the driver for providing a waveform to the driver. The driver then provides the clock signal based on this input waveform. Additionally, the gate is situated between the generator and the driver. The gate, based on the output of the sensing circuit, can then prevent the waveform from being provided to the driver.

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patent: 5461652 (1995-10-01), Hongo
patent: 5603037 (1997-02-01), Aybay
patent: 5625807 (1997-04-01), Lee et al.

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