Memory clock slowdown synthesis circuit

Details Memory clock slowdown synthesis circuit Memory clock slowdown synthesis circuit

2006-05-09

2006-05-09

Callahan, Timothy P. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Particular stable state circuit

C327S200000, C327S407000, C327S159000, C326S038000, C326S040000

Reexamination Certificate

active

07042263

ABSTRACT:
Circuits, methods, and apparatus for reducing power on a graphics processor integrated circuit by generating two memory clock signals, reducing the frequency of one under certain conditions, and maintaining the frequency of the other. To reduce skew and jitter between these two memory clocks, and to ensure that they remain in phase, a synchronizer circuit is used by an exemplary embodiment of the present invention. The synchronizer circuit is also useful as a general application clock generator.

REFERENCES:
patent: 5818366 (1998-10-01), Morley
patent: 6362680 (2002-03-01), Barnes
patent: 6472904 (2002-10-01), Andrews et al.
patent: 6525565 (2003-02-01), Young et al.
patent: 6614371 (2003-09-01), Zhang
patent: 6777980 (2004-08-01), Young et al.

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