Method and an apparatus to generate static logic level output
Method and apparatus for a configurable latch
Method and apparatus for enabling a stand alone integrated...
Method and apparatus for glitch protection for input buffers...
Method and apparatus for latching a clocked data signal
Method and apparatus for latching data within a digital system
Method and apparatus for providing noise immunity for a...
Method and apparatus for reducing charge sharing and the...
Method and apparatus for reducing the vulnerability of...
Method and apparatus for reducing the vulnerability of...
Method and apparatus for test mode entry during power up
Method and apparatus to delay signal latching
Method and circuit for eliminating hold time violations in synch
Method and circuit for optimizing power consumption in a...
Method and circuit of soft start and of power monitor for IC...
Method and circuitry for preserving a logic state
Method and device for the reduction of latch insertion delay
Method and system for providing startup delay
Method and system for providing startup delay
Method and system for reducing glitch effects within...