Method and device for the reduction of latch insertion delay

Details Method and device for the reduction of latch insertion delay Method and device for the reduction of latch insertion delay

1998-05-19

2000-08-22

Zweizig, Jeffrey

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Particular stable state circuit

327211, 327214, H03K 3356

Patent

active

061078522

ABSTRACT:
A method and device are disclosed for the reduction of the penalty associated with inserting a latch in a circuit which is utilized to implement an integrated circuit in a data-processing system. A semiconductor device is disclosed which includes a main latch circuit, a feedback latch circuit and an output terminal. The main latch circuit is capable of receiving an input data signal and an input clock signal. The main latch circuit generates a latch output signal in response to the input data and clock signals. The feedback latch circuit is capable of receiving the latch output signal from the main latch circuit and storing the latch output signal. The feedback latch circuit is capable of generating a feedback latch circuit output signal which is received by the main latch circuit to maintain the latch output signal. The output terminal of the device is coupled to the feedback latch circuit for outputting a device output signal which is equal to the feedback latch circuit output signal.

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patent: 5767716 (1998-06-01), Ko

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