Method and circuit for eliminating hold time violations in synch

Details Method and circuit for eliminating hold time violations in synch Method and circuit for eliminating hold time violations in synch

1996-05-02

1999-07-06

Pihulic, Daniel T.

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Particular stable state circuit

H03K 3037

Patent

active

H00017965

ABSTRACT:
Circuits and methods for eliminating hold time violations are disclosed. A DE-type flip-flop latches a data input signal on a data input terminal a fraction of a clock period before a triggering edge of the clock signal. The DE-type flip-flop provides a data output signal for a full clock period beginning after the triggering edge of the clock signal. The DE-type flip-flop includes a latch having its data output terminal coupled to the data input terminal of a flip-flop. The flip-flop clock input pin and the latch enable terminal of the latch are connected to a clock line. The DE-type flip-flop used in place of a standard flip-flop, in which a hold time violation occurs, eliminates the hold time violation.

REFERENCES:
patent: 4209715 (1980-06-01), Aoki
patent: 4785297 (1988-11-01), Sekiya
patent: 5004933 (1991-04-01), Widener
patent: 5025174 (1991-06-01), Shikata

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