Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Particular stable state circuit
Reexamination Certificate
2002-09-26
2004-12-14
Wells, Kenneth B. (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Signal converting, shaping, or generating
Particular stable state circuit
C327S212000
Reexamination Certificate
active
06831495
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to logic circuits, and more particularly to a method and circuit for optimizing power consumption in a flip-flop.
BACKGROUND OF THE INVENTION
Most VLSI designs have numerous flip-flops integrated within them. Typically, flip-flops are critical to the overall performance of this design. Conventional flip-flops are generally large, power hungry and a significant amount of time is spent optimizing their configuration. It is desirable therefore to minimize the power used by flip-flops in a circuit design. It is known that one way to save power is to shut off sections of the design. For example, one way to save power is to utilize clock gating to disable the clock when it is not used. Also, in an effort to save or minimize standby power, some designs have resorted to disabling non-used sections of the design from the power supply. However, disabling power supply generally results in a loss of stored data in the volatile memory elements.
A solution for the problem of data loss during a standby mode is to transfer the data, or state of a latch, to an on-chip memory before the latch is disconnected from the power supply. Examples of on-chip memory include DRAM, SRAM, or Flash memory. This enables the powering down of the latch to conserve power. This technique, however, requires an auxiliary device, i.e., the on-chip memory.
Accordingly, what is needed is a method and circuit for optimizing power consumption in a flip-flop. The method and circuit should also be cost effective, save space, and easily implemented in existing circuit designs. The present invention addresses such needs.
SUMMARY OF INVENTION
A flip-flop is disclosed. The flip-flop includes a first latch for receiving at least one bit and a second latch coupled to the first latch for storing the at least one bit from the first latch. The size of the second latch is minimized to reduce power consumption. The flip-flop also includes a multiplexor coupled to the first latch and to the second latch for outputting the at least one bit from the first latch when a clock to the multiplexor is active and for outputting the at least one bit from the second latch when the clock is inactive.
A system and method in accordance with the present invention optimize power consumption in a flip-flop through the use of a multiplexor for the output function. As a result, the size of the slave latch can be minimized, which reduces the overall power consumption of the flip-flop and its associated clock tree.
REFERENCES:
patent: 4686394 (1987-08-01), Lam
patent: 4806786 (1989-02-01), Valentine
patent: 5250852 (1993-10-01), Ovens et al.
patent: 5378934 (1995-01-01), Takahashi et al.
patent: 5926487 (1999-07-01), Chappell et al.
patent: 6300809 (2001-10-01), Gregor et al.
Correale, Jr. Anthony
Kindl Brian Thomas
Lynch Robert James
International Business Machines - Corporation
Reid Scott W.
Sawijer Law Group, LLP
Wells Kenneth B.
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