Double edge triggered flip-flop
Double edge-triggered flip-flops
Double-edge-triggered flip-flop providing two data...
Drive circuit detecting slow signal transition
Dual clock D type flip-flop
Dual data rate flip-flop
Dual edge D flip flop
Dual edge-triggered flip-flop design with asynchronous...
Dual latch clocked LSSD and method
Dual latch clocked LSSD and method
Dual operational mode CML latch
Dual operational mode CML latch
Dual rail dynamic flip-flop with single evaluation path
Dual tristate path output buffer control
Dynamic circuit for capturing data with wide reset tolerance
Dynamic circuit for high-speed operation
Dynamic circuits and static latches with low power dissipation
Dynamic circuits and static latches with low power dissipation
Dynamic CMOS register with a self-tracking clock
Dynamic flip flop