Dynamic circuit for high-speed operation

Details Dynamic circuit for high-speed operation Dynamic circuit for high-speed operation

1997-06-17

1999-05-04

Lam, Tuan T.

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Particular stable state circuit

327211, 327212, 327218, 326 28, 326 97, H03K 3356, H03K 17687

Patent

active

059007583

ABSTRACT:
A dynamic latch circuit or a dynamic flip-flop circuit of the present invention includes a transfer gate to be controlled by a clock and provided with a complementary configuration using a P-channel and an N-channel MOS (Metal Oxide Semiconductor) transistor. The transfer gate allows the individual node included in the circuit to fully swing between a high potential power source and a low potential power source. This causes a minimum of decrease to occur in an ON current for driving the respective node and thereby realizes high-speed operation. Further, the balance of the rising time and falling time of an output signal is improved, reducing the deviation of the duty of the output signal from 50%. The circuit is therefore operable with sufficient operation margins at positive- and negative-going edges. Consequently, the entire macrocircuit using the circuit of the present invention can have its operation frequency and therefore power consumption lowered.

REFERENCES:
patent: 5140194 (1992-08-01), Okitaka
patent: 5459421 (1995-10-01), Shaw
J. Yuan et al., "High-Speed CMOS Circuit Technique", IEEE Journal of Solid-State Circuits, vol. 24 No. 1, Feb. (1989), pp. 62-70.

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