Dual operational mode CML latch

Details Dual operational mode CML latch Dual operational mode CML latch

2008-04-15

2008-04-15

Wells, Kenneth B. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Particular stable state circuit

C327S203000, C327S211000, C327S212000, C327S215000

Reexamination Certificate

active

07358787

ABSTRACT:
A dual purpose current mode logic (“CML”) latch circuit is provided which includes a CML latch operable to receive at least a pair of differential input data signals and at least one clock signal. The CML latch is operable to generate at least one output signal in accordance with the states of the pair of input differential data signals. A mode control device is operable to receive a mode control signal to operate the CML latch as a buffer or as a latch. In such way, when the mode control signal is inactive, the CML latch generates and latches the output signal at a timing determined by the at least one clock signal, and when the mode control signal is active the CML latch generates the output signal such that the output signal changes whenever the states of the pair of differential input data signals change.

REFERENCES:
patent: 4274017 (1981-06-01), Carter et al.
patent: 6850104 (2005-02-01), Fattaruso
SE Bello et al., “Hybrid Differential Cascode Current Switch Shift Register Latch,”IBM Technical Disclosure Bulletin, Jul. 1987, pp. 864-866.

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