Dynamic CMOS register with a self-tracking clock

Details Dynamic CMOS register with a self-tracking clock Dynamic CMOS register with a self-tracking clock

1997-09-08

1999-08-10

Callahan, Timothy P.

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Particular stable state circuit

327210, 327212, 327200, 327199, 326 94, 326 95, 326 98, H03K 1917

Patent

active

059364491

ABSTRACT:
A dynamic CMOS register implemented on a silicon die that requires the use of only two input signals, a data-in signal and an inverse clock signal. Each embodiment includes a self-timed clock circuit having a CMOS PNN tier of FETs with a P channel and two N channels connected serially (sources of P channel at one end connected to bus and N channel at the other end connected to ground, and gate of end N channel connected to bus), a first inverter to receive inverse clock with output connected to gate of P channel, a second inverter connected to drain of P channel, and a NOR gate with one input receiving inverse clock, second input connected to output of second inverter and output connected to gate of center N channel. In one embodiment, a single self-timed clock circuit interfaces with and controls a plurality of CMOS registers. In each of two other embodiments, the self-timed clock circuit interfaces with one or two additional CMOS PNN tiers of FETs with a P channel and two N channels connected serially and an output latch forming a CMOS register that operates in a precharge phase and an evaluation phase.

REFERENCES:
patent: 4554467 (1985-11-01), Vaughn
patent: 4800300 (1989-01-01), Walters, Jr.
patent: 5561694 (1996-10-01), Fifield
patent: 5796282 (1998-08-01), Sprague

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