Dual data rate flip-flop

Details Dual data rate flip-flop Dual data rate flip-flop

2007-07-10

2007-07-10

Wells, Kenneth B. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Particular stable state circuit

C327S211000

Reexamination Certificate

active

11067513

ABSTRACT:
A flip-flop is configured to operate either in a double data-rate mode or a normal mode. When configured to operate in the double data-rate mode, the flip-flop outputs data on both edges of the applied clock. When configured to operate in the normal mode, the flip-flop outputs data on either the rising or falling edges of the applied clock. In the double data-rate mode, when a first latch disposed in the flip-flop operates in a sampling mode, the second latch disposed in the flip-flop operates in a holding mode to supply the output data, and when the second latch operates in the sampling mode, the first latch operates in the holding mode to supply the output data. Accordingly, with each of the rising or falling edge of the clock, one of the latches supplies an output data.

REFERENCES:
patent: 4811364 (1989-03-01), Sager et al.
patent: 4873456 (1989-10-01), Olisar et al.
patent: 5589787 (1996-12-01), Odinot
patent: 6300809 (2001-10-01), Gregor et al.
patent: 6317842 (2001-11-01), Nguyen
patent: 6362680 (2002-03-01), Barnes
patent: 6691272 (2004-02-01), Azim
patent: 6938225 (2005-08-01), Kundu
patent: 6943605 (2005-09-01), Thadikaran et al.

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