Dual rail dynamic flip-flop with single evaluation path

Details Dual rail dynamic flip-flop with single evaluation path Dual rail dynamic flip-flop with single evaluation path

2000-04-02

2001-07-24

Tran, Toan (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Particular stable state circuit

C327S211000

Reexamination Certificate

active

06265923

ABSTRACT:

BACKGROUND
1. Field of Invention
This invention relates generally to digital circuits and specifically to dynamic flip-flops.
2. Description of Related Art
Dynamic logic gates operate in two phases: a pre-charge phase and an evaluation phase. During the pre-charge phase, the dynamic logic gate drives its output terminal to a first logic state. Then, during the evaluation phase, the dynamic logic gate causes its output signal to either remain at the first logic state or transition to a second logic state, depending upon the dynamic logic gates' input signal(s). The dynamic logic gate returns its output signal to the first logic state during the next pre-charge phase. By forcing its output signal to the same logic state prior to each evaluation phase, the dynamic logic gate need only allow logic transitions in one direction during the evaluation phase. As a result, the dynamic logic gate may be optimized to favor logic transitions from the first logic state to the second logic state during the evaluation phase, which in turn improves performance over static logic gates which allow logic transitions in both directions, and thus cannot be optimized for logic transitions in one direction.
In the past, static flip-flops were typically used to drive dynamic logic gates. However, in addition to allowing logic transitions in both directions, a static flip-flop provides an output signal that requires a certain amount of time to become stable, and therefore must be synchronized with the two-phase operation of dynamic logic gates. The time and uncertainty involved in synchronizing the output signal of a static flip-flop with the input signal requirements of a dynamic logic gate undesirably limits the performance of dynamic logic.
More recently, a dynamic flip-flop was disclosed in U.S. Pat. No. 5,825,224 issued to Klass and assigned to the assignee of the present invention, that eliminates the time penalty associated using static flip-flops to drive dynamic logic gates.
FIG. 1
is a block diagram of a dual-rail dynamic flip-flop
10
of the type disclosed in U.S. Pat. No. 5,825,224, which is incorporated by reference herein. The dynamic flip-flop
10
includes a first input latch
11
with a shut-off circuit
12
, a second input latch
13
with a shut-off circuit
14
, and output latches
15
and
16
. The first and second input latches
11
and
13
are clocked with a clock signal CLK. The first input latch
11
receives a data signal D, and in response thereto provides an output signal to the first output latch
15
via node OUT
1
. The second input latch
13
receives complementary data signal {overscore (D)} via inverter INV
1
, and in response thereto provides an output signal to the second output latch
16
via node OUT
2
N. The shut-off circuit
12
prevents the first input latch
11
from further sampling signal D when output node OUT
2
N transitions to logic low, and the shut-off circuit
14
disables the second input latch
13
from further sampling signal {overscore (D)} when output node OUT
1
transitions to logic low. Together, the shut-off circuits
12
and
14
implement edge-triggered data sampling for the dual evaluation paths on node OUT
1
and OUT
2
N, respectively.
Referring also to
FIG. 2
, when the clock signal CLK is logic low, the dynamic flip-flop circuit
10
is in the pre-charge phase. The input latches
11
and
13
pre-charge their respective output nodes OUT
1
and OUT
2
N to logic high. The logic high level at node OUT
1
is inverted by output latch
15
, which in turn drives the Q output signal to logic low. The logic high level at node OUT
2
N is inverted by output latch
16
, which in turn drives the {overscore (Q)} output signal to logic low. On the rising edge of CLK, the dynamic flip-flop
10
enters the evaluation phase. The first input latch
11
samples the data signal D and, in response thereto, causes its output node OUT
1
to either remain logic high or to transition to logic low. The output latch
15
inverts the logic state at node OUT
1
to generate the Q output signal. Similarly, the second input latch
13
samples the complementary data signal D and, in response thereto, causes its output node OUT
2
N to either remain logic high or to transition to logic low. The output latch
16
inverts the logic state at node OUT
2
N to generate the {overscore (Q)} output signal.
FIG. 3
is a schematic diagram of the dynamic flip-flop circuit
10
disclosed in U.S. Pat. No. 5,825,224. The first input latch
11
includes p-channel transistors PC
1
and K
2
, n-channel transistors S
1
and N
1
, and inverters INV
2
and INV
3
, where the transistor S
1
and inverters INV
2
and INV
3
implement the shut-off circuit
12
. The second input latch
13
includes p-channel transistors K
1
and PC
2
, n-channel transistors S
2
and N
2
, and inverters INV
4
and INV
5
, where the transistor S
2
and inverters INV
4
and INV
5
implement the shutoff circuit
14
. The input latches
11
and
13
share an n-channel transistor EVAL. The first input latch
11
receives the data signal D at the gate of its input transistor N
1
, and the second input latch
13
receives the complemented data signal {overscore (D)} via inverter INV
1
at the gate of its input transistor N
2
. The output latch
15
includes an inverter INV
6
and a n-channel transistor N
3
, and the output latch
16
includes an inverter INV
7
and a n-channel transistor N
4
.
During the pre-charge phase, the logic low CLK signal turns off the evaluation transistor EVAL and turns on the pre-charge transistors PC
1
and PC
2
. With the non-conducting evaluation transistor isolating nodes OUT
1
N and OUT
2
N from the low voltage rail (e.g., ground potential), the pre-charge transistors PC
1
and PC
2
quickly pre-charge respective nodes OUT
1
N and OUT
2
N toward the V
DD
rail. The resultant logic high levels at nodes OUT
1
N and OUT
2
N propagate through respective inverters INV
6
and INV
7
, which in turn cause respective Q and {overscore (Q)} output signals to be logic low during the pre-charge phase (see the timing diagram of FIG.
2
). The logic high levels at nodes OUT
1
N and OUT
2
N maintain respective p-channel keeper transistors K
1
and K
2
in a non-conducting state, and also turn on respective shut-off transistors S
1
and S
2
.
When the clock signal CLK transitions to logic high, the evaluation transistor EVAL turns on and discharges node CGND to logic low, thereby commencing the evaluation phase. The logic high clock CLK also turns off the pre-charge transistors PC
1
and PC
2
. If the data signal D is logic high when the evaluation phase begins, the first input transistor N
1
turns on while the second input transistor N
2
turns off. Output node OUT
1
N discharges to logic low through transistors S
1
, N
1
and EVAL, while the non-conducting input transistor N
2
maintains output node OUT
2
N at logic high. The inverter INV
6
inverts the logic low level at node OUT
1
N to drive the Q output signal to logic high, and the inverter INV
7
inverts the logic high level at node OUT
2
N to keep the {overscore (Q)} output signal at logic low. The logic low level at node OUT
1
N turns off the shut-off transistor S
2
via inverters INV
4
and INV
5
to prevent the second input latch
13
from further data sampling. The logic low signal at node OUT
1
N also turns on transistor K
1
, which maintains node OUT
2
N at logic high to reduce charge loss.
Conversely, if the data signal D is logic low, the input transistor N
1
turns off and thus does not discharge node OUT
1
N toward ground potential. The resulting logic high signal at node OUT
1
N is inverted by INV
6
to drive the Q output signal to logic low. The logic low data signal D is inverted by INVL to generate a logic high complementary data signal {overscore (D)}, which turns on the second input transistor S
2
to discharge the second output node OUT
2
N to logic low. In response thereto, the output latch
16
drives its {overscore (Q)} output signal to logic high, as illustrated by the dashed {overscore (Q)} waveform in FIG.
2
. The lo

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