Dual clock D type flip-flop

Details Dual clock D type flip-flop Dual clock D type flip-flop

1999-02-01

2001-11-20

Lam, Tuan T. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Particular stable state circuit

C327S212000

Reexamination Certificate

active

06320442

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates generally to flip-flops. More particularly, it relates to a dual clock D type flip-flop circuit capable of operating on two clock signals with respective two input data signals.
2. Background of Related Art
A D type flip-flop is an integrated circuit device which latches for output an input signal based on a rising or falling edge of an input clock signal. Many circuits often include a D type flip-flop, which is depicted schematically in FIG.
4
.
In particular,
FIG. 4
shows a schematic symbol for a conventional D type flip-flop
400
. The D type flip-flop
400
includes one input signal D, an output signal Q, and one clock signal CLK. The D type flip-flop
400
further includes the ability to have its output Q preset with a predetermined condition upon reset using a preset PRE line, as well as the ability to be reset using a clear CLR line.
D type flip-flops have been in existence for decades, and have many, many uses, most typically in latching a data signal for output based on an edge of a clock signal. However, there are situations wherein it is desired to provide a single output event based on the occurrence of two input signals each having its own clock signal.
There are cases, especially in state machines and interface logic, when it is desirable to build a flip-flop device which is capable of switching on the edges of two different clocks. For instance, such a device would be useful in a state machine which is to be turned on when one particular condition holds true at the time of a first rising clock signal, e.g., on a first clock edge, and turned off when some other condition holds true at the time of a second clock signal, e.g., on a falling clock edge.
A second example of a situation for using a flip-flop inputting two separate clock signals would be if gated clocks are used for two different blocks of a device, and there is an inherent (and not very controllable) skew between the two clock signals. Then, if some signal is generated in one block and used in another block, it would be useful to set this signal based on one edge (e.g., a rising edge) of a clock signal to the first block, and resetting it on the edge of a clock signal to the second block.
Yet another example would be if an interface device needs to toggle a signal on the rising edges of two asynchronous clock signals. In this case, instead of synchronizing every input signal coming from an independently clocked device, it would be convenient to use a dual clock D flip-flop in accordance with the principles of the present invention.
There is thus a need for a D type flip-flop device which is capable of operation based on two input signals clocked independently by two clock signals.
SUMMARY OF THE INVENTION
In accordance with the principles of the present invention, a dual clock flip-flop comprises a first single clock flip-flop adapted to change a state of an output signal thereof based on an occurrence of an event on a data line input thereto as determined by a clock signal input thereto. A second single clock flip-flop is adapted to change a state of an output signal thereof based on an occurrence of an event on a data line input thereto as determined by a clock signal input thereto. A logic circuit provides an output data signal of the dual clock flip-flop comprising an exclusive OR of the output signal of the first single clock flip-flop and the output signal of the second single clock flip-flop.
In accordance with another aspect of the present invention, a dual clock D type flip-flop comprises means for outputting an active signal after an occurrence of a first event on a first data input line triggered by an edge of a first clock signal. The dual clock D type flip-flop further comprises means for maintaining a state of the output active signal until a second event is detected on a second data input line based on a second clock signal, and means for deactivating the output signal upon the detection of the second event on the second data input line based on the second clock signal.
A method of indicating a detection of two signal events in accordance with the principles of the present invention comprises providing an active output signal upon a first event of an edge of a first clock signal occurring during an activation of a first data signal. The output signal is deactivated upon a second event of an edge of a second clock signal occurring during an activation of a second data signal. After each first event, the output signal is prevented from being affected by the first clock signal and the first data signal until after a subsequent second event has occurred. After each second event, the output signal is prevented from being affected by the second clock signal and the second data signal until after a subsequent first event has occurred.


REFERENCES:
patent: 5327019 (1994-07-01), Kluch
patent: 5894213 (1999-04-01), Nakamura
patent: 5896052 (1999-04-01), Gujral et al.

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