Dynamic circuits and static latches with low power dissipation

Details Dynamic circuits and static latches with low power dissipation Dynamic circuits and static latches with low power dissipation

1997-12-24

2000-05-30

Lam, Tuan T.

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Particular stable state circuit

327208, H03K 3356

Patent

active

060695129

ABSTRACT:
A half latch for latching a voltage at a domino gate output with reduced crossbar current duty cycle, comprising a CMOS inverter with input connected to the domino gate output, a first pMOSFET having a gate and drain connected to ground and having a source coupled to the source of the nMOSFET of the CMOS inverter to prevent the source voltage of the nMOSFET from approaching ground, and a second pMOSFET having a gate connected to the output of the CMOS inverter and having a drain connected to the input of the CMOS inverter.

REFERENCES:
patent: 4578600 (1986-03-01), Magee
patent: 4791321 (1988-12-01), Tanaka et al.
patent: 5371420 (1994-12-01), Nakao
"Field Effect Transistor" by Neudeck et la., pp. 119-120, 130-134, 1990.

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